Semiconductor power modules and devices

• US 8,952,750 B2
• Filed: 12/19/2013
• Issued: 02/10/2015
• Est. Priority Date: 02/24/2012
• Status: Active Grant

• Current Assignee: Transphorm Technology, Inc. (Kohlberg Kravis Roberts & Company LP)
• Original Assignee: Transphorm, Inc (Kohlberg Kravis Roberts & Company LP)
• Inventors: Wu, Yifeng
• Primary Examiner(s): JAGER, RYAN C
• Application Number:
  US14/134,878
• Publication Number:
  US 20140103989A1
• Time in Patent Office: 418 Days
• Field of Search: 327/419, 327/566, 257/503, 257/506
• US Class Current: 327/566
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/12 Mountings, e.g. non-detachable insulating substrates
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/117 Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H03K 17/164 : using parallel switching arrangements
• CPC Class Codes: H03K 2217/0045 : Full bridges, determining the direction of the current through the load
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 1/0263 : High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board H05K1/0293 takes precedence
• CPC Class Codes: H05K 1/162 : incorporating printed capacitors
• CPC Class Codes: H05K 2201/10015 : Non-printed capacitor
• CPC Class Codes: H05K 2201/10166 : Transistor
• CPC Class Codes: H05K 2201/10545 : Related components mounted on both sides of the PCB

Abstract

An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Claims

1. A half bridge, comprising:

a first switch encased in a first package, the first package comprising a first conductive portion having a first area, the first transistor being mounted over the first conductive portion;

a second transistor encased in a second package, the second package comprising a second conductive portion having a second area, the second transistor being mounted over the second conductive portion; and

a substrate comprising an insulating layer and a metal layer;

wherein

the first package is on a first side of the substrate and the second package is on a second side of the substrate; and

the first package is opposite the second package, with at least 50% of the first area of the first conductive portion being opposite the second area of the second conductive portion.

2. The half bridge of claim 1, the first package having a source lead and the second package having a drain lead, wherein the source and drain leads are electrically connected to one another.

3. The half bridge of claim 1, wherein the first switch has a first electrode which is electrically connected to the first conductive portion, and the second switch has a second electrode which is electrically connected to the second conductive portion.

4. The half bridge of claim 3, wherein the second electrode is a source electrode of the second switch.

5. The half bridge of claim 4, wherein the first electrode is a drain electrode of the first switch.

6. The half bridge of claim 1, wherein the first switch or the second switch comprises a III-Nitride transistor.

7. The half bridge of claim 1, wherein the first switch or the second switch comprises a lateral transistor.

8. The half bridge of claim 1, wherein the first switch comprises a first transistor and a second transistor, a source of the first transistor is electrically connected to a drain of the second transistor, and a gate of the first transistor is electrically connected to a source of the second transistor.

9. The half bridge of claim 8, wherein the first transistor is a high-voltage depletion-mode transistor, and the second transistor is a low-voltage enhancement-mode transistor.

10. The half bridge of claim 9, wherein low-voltage enhancement-mode transistor is mounted directly on top of the source of the high-voltage depletion-mode transistor.

11. The half bridge of claim 8, wherein the first transistor is a lateral transistor and the second transistor is a vertical transistor.

12. The half bridge of claim 1, wherein the metal layer comprises a metal mount.

13. The half bridge of claim 12, wherein the metal mount is connected to or is part of a heat sink.

14. A half bridge, comprising:

a capacitor comprising an insulating layer between a first conductive portion and a second conductive portion, the first conductive portion having a first area and the second conductive portion having a second area;

a first transistor encased in a first package, the first package comprising the first conductive portion; and

a second transistor encased in a second package, the second package comprising the second conductive portion;

wherein

the first package is on a first side of the insulating layer and the second package is on a second side of the insulating layer.

15. The half bridge of claim 14, wherein the first package is opposite the second package, with at least 50% of the first area of the first conductive portion being opposite the second area of the second conductive portion.

16. The half bridge of claim 14, the first package having a drain lead and the second package having a source lead, wherein the source lead of the second package is electrically connected to the second conductive portion.

17. The half bridge of claim 16, wherein the drain lead of the first package is electrically connected to the first conductive portion.

18. A method of operating a half bridge circuit comprising a first switch encased in a first package and a second switch encased in a second package, the first switch and the second switch being on opposite sides of an insulating layer, the method comprising:

biasing a drain of the first switch at a voltage of at least 300 Volts relative to a source of the second switch;

biasing the first switch on and biasing the second switch off, thereby causing a current of at least 3 Amps to flow through the first switch and causing the second switch to block a voltage; and

at a first time switching the first switch off, causing the current to flow through the second switch and causing the first switch to block a voltage;

wherein

the switching of the first switch comprises hard-switching of the first switch at a switching rate of at least 100 Volts/nanosecond.

19. The method of claim 18, wherein the first switch and the second switch each comprise one or more transistors.

20. The method of claim 18, further comprising at a second time switching the first switch from off to on, causing the current to flow through the first switch and causing the second switch to block a voltage.

21. The method of claim 20, wherein the second time is after the first time.

22. The method of claim 18, further comprising connecting the half bridge circuit to an electrical load, wherein the current flows through the electrical load.

23. The method of claim 18, wherein the drain of the first switch is biased at a voltage of at least 400 Volts relative to the source of the second switch.

24. A half bridge configured to be connected to an electrical load, the half bridge comprising:

a first switch encased in a first package and a second switch encased in a second package, the first switch comprising a first source and the second switch comprising a second drain, the first source being electrically connected to the second drain;

wherein

the first switch and the second switch are on opposite sides of a metal mount; and

the half bridge is operable to hard-switch a voltage of at least 300 Volts across the electrical load at a switching rate of at least 100 Volts/nanosecond while a current of at least 3 Amps flows through the electrical load.

25. The half bridge of claim 24, wherein the current is at least 6 Amps.

26. The half bridge of claim 24, wherein the metal mount is connected to or is part of a heat sink.

27. The half bridge of claim 24, further comprising an insulating layer, wherein the first switch and the second switch are on opposite sides of the insulating layer.

28. The half bridge of claim 24, wherein the first switch comprises a first transistor and a second transistor, the first source is a source of the second transistor, a source of the first transistor is electrically connected to a drain of the second transistor, and a gate of the first transistor is electrically connected to the source of the second transistor.

29. The half bridge of claim 28, wherein the first transistor is a high-voltage depletion-mode transistor, and the second transistor is a low-voltage enhancement-mode transistor.

30. The half bridge of claim 29, wherein low-voltage enhancement-mode transistor is mounted directly on top of the source of the high-voltage depletion-mode transistor.

31. The half bridge of claim 28, wherein the first transistor is a lateral transistor and the second transistor is a vertical transistor.