Semiconductor memory device
First Claim
1. A semiconductor memory device comprising:
- a memory cell array that includes a word line extending in a row direction, a bit line group containing a plurality of bit lines extending in a column direction, and memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of the word line and the bit line group;
a read circuit configured to read out data from the memory cells through the bit lines; and
a bit line precharge/discharge circuit disposed between the memory cell array and the read circuit, and configured to charge or discharge the bit lines;
the memory cell having different connection states including a state in which a first terminal of the transistor is not electrically connected to any one of the plurality of bit lines belonging to the bit line group and states in which the first terminal is electrically connected only to a specific one of the plurality of bit lines, the first terminal being a source or a drain of the transistor, andan active area serving as a gate of the transistor being continuously formed in arrangement areas of the plurality of bit lines of the bit line group and spaces between the bit lines, when viewed in a stacking direction that is perpendicular to the row direction and the column direction.
1 Assignment
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Accused Products
Abstract
A semiconductor memory device according to an embodiment includes a memory cell array including memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of a word line and a bit line group, the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the bit lines, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the bit lines of the bit line group and spaces between the bit lines.
6 Citations
20 Claims
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1. A semiconductor memory device comprising:
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a memory cell array that includes a word line extending in a row direction, a bit line group containing a plurality of bit lines extending in a column direction, and memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of the word line and the bit line group; a read circuit configured to read out data from the memory cells through the bit lines; and a bit line precharge/discharge circuit disposed between the memory cell array and the read circuit, and configured to charge or discharge the bit lines; the memory cell having different connection states including a state in which a first terminal of the transistor is not electrically connected to any one of the plurality of bit lines belonging to the bit line group and states in which the first terminal is electrically connected only to a specific one of the plurality of bit lines, the first terminal being a source or a drain of the transistor, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the plurality of bit lines of the bit line group and spaces between the bit lines, when viewed in a stacking direction that is perpendicular to the row direction and the column direction. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory, comprising:
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a memory cell array that includes a word line extending in a row direction, a bit line group containing a plurality of bit lines extending in a column direction, and memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of the word line and the bit line group; and a read circuit configured to read out data from the memory cells through the bit lines, the memory cell having different connection states including a state in which a first terminal of the transistor is not electrically connected to any one of the plurality of bit lines belonging to the bit line group and states in which the first terminal is electrically connected only to a specific one of the plurality of bit lines, the first terminal being a source or a drain of the transistor, and the read circuit including an encode circuit provided with NOR gates between each of inputs and outputs, and configured to read data from the memory cells by passing a potential of the bits through the encode circuit. - View Dependent Claims (9)
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10. A semiconductor memory device, comprising:
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a memory cell array that includes a word line extending in a row direction, bit line groups containing a plurality of bit lines extending in a column direction, and memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of the word line and the bit line group; and a read circuit configured to read out data from the memory cells through the bit lines, the memory cell having different connection states including a state in which a first terminal of the transistor is not electrically connected to any one of the plurality of bit lines belonging to the bit line group and states in which the first terminal is electrically connected only to a specific one of the plurality of bit lines, the first terminal being a source or a drain of the transistor, and the memory cell array including a shield line extending in the column direction and formed between adjacent bit line groups, the shield line being electrically connected to a ground line or a power source line. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification