Nonvolatile memory device and read method thereof

• US 8,953,376 B2
• Filed: 02/21/2012
• Issued: 02/10/2015
• Est. Priority Date: 03/03/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nam, Sang-Wan, Yoon, Chiweon, Kim, Jung-Soo
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US13/401,151
• Publication Number:
  US 20120224426A1
• Time in Patent Office: 1,085 Days
• Field of Search: 365/185.11, 365/185.17, 365/185.18, 365/185.23, 365/185.2
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

According to example embodiments, a read method of a nonvolatile memory device includes Disclosed is a read method of a nonvolatile memory device which includes selecting one of a plurality of vertical strings in a nonvolatile memory device, judging a channel length between a common source line and a selected one of the plurality of vertical strings, selecting a sensing manner corresponding to the judged channel length, and performing a sensing operation according to the selected sensing manner. The plurality of vertical strings may extend in a direction perpendicular to a substrate of the nonvolatile memory device.

Claims

1. A read method of a nonvolatile memory device comprising:

selecting one of a plurality of vertical strings in a nonvolatile memory device, the plurality of vertical strings extending in a direction perpendicular to a substrate of the nonvolatile memory device;

judging a channel length between a common source line and the selected one of the plurality of vertical strings;

selecting a sensing manner corresponding to the judged channel length; and

performing a sensing operation according to the selected sensing manner.

2. The read method of claim 1, wherein

the nonvolatile memory device includes two of the plurality of vertical strings connected with a bit line between at least two word line cuts.

3. The read method of claim 1, wherein

the nonvolatile memory device includes the plurality of vertical strings arranged in a zigzag structure between at least two word line cuts.

4. The read method of claim 3, wherein at least one corresponding vertical string of the plurality of vertical strings comprises:

at least one string selection transistor connected between a bit line and a channel of the corresponding vertical string,

the at least one string selection transistor including a gate connected with a string selection line;

a plurality of cell transistors connected in series to form a channel of the corresponding vertical string,

the plurality of cell transistors containing gates connected with word lines, respectively; and

at least one ground selection transistor connected between the channel of the corresponding vertical string and the common source line,

the at least one ground selection transistor including a gate connected with a ground selection line,

wherein the at least one string selection transistor, the plurality of cell transistors, and the at least one ground selection transistor are stacked on the substrate.

5. The read method of claim 4, wherein the sensing operation includes controlling a bias voltage of the selected vertical string according to the selected sensing manner.

6. The read method of claim 5, wherein the sensing operation includes:

controlling bias voltages of the word lines according to the selected sensing manner.

7. The read method of claim 5, wherein the sensing operation includes:

controlling a voltage of the ground selection line according to the selected sensing manner.

8. The read method of claim 4, wherein the sensing operation includes:

controlling a develop time according to the selected sensing manner.

9. The read method of claim 8, wherein, if the judged channel length is over a reference value, the sensing operation includes:

making the develop time longer than a target develop time, according to the selected sensing manner.

10. The read method of claim 4, wherein the sensing operation includes:

controlling a bias voltage of the selected vertical string and a develop time of the sensing operation according to the selected sensing manner.

11. A nonvolatile memory device comprising:

a memory cell array including a plurality of memory blocks, each memory block including

a plurality of vertical strings extending in a direction perpendicular to a substrate;

an address decoder configured to decode an input address to generate a block selection signal;

a block gating unit configured to select one of the plurality of memory blocks in response to the block selection signal;

a read/write circuit connected with the memory cell array via bit lines and configured to exchange data with an external device; and

a control logic configured to control the block gating unit, the address decoder, and the read/write circuit,

wherein the control logic is configured to perform a read operation using a sensing manner selected according to a channel length between a selected vertical string and a common source line.

12. The nonvolatile memory device of claim 11, wherein each of the vertical strings includes at least one dummy cell containing a gate connected with a dummy word line.

13. The nonvolatile memory device of claim 11, wherein each of the vertical strings comprises:

an upper string selection transistor connected with one end of a bit line and including a gate connected with an upper string selection line; and

a lower string selection transistor connected between the upper string selection transistor and a channel of a corresponding vertical string and including a gate connected with a lower string selection line.

15. The nonvolatile memory device of claim 11, wherein each of the memory blocks includes at least two vertical strings in a zigzag pattern between at least two word line cuts.

16. The nonvolatile memory device of claim 11, wherein, in each memory block,

the plurality of vertical strings include a first plurality of vertical strings and a second plurality of vertical strings, and

the first plurality of vertical strings have a shorter channel length to an adjacent common source line compared to the second plurality of vertical strings.

17. The nonvolatile memory device of claim 11, wherein, in each memory block,

the plurality of vertical strings include a first vertical string and a second vertical string,

the first and second vertical strings have different channel lengths to an adjacent common source line,

the first and second vertical strings are connected to different bit lines,

the first and second vertical strings are connected to a same ground select line, and

the control logic is configured to at least one of,

adjust a value of a read pass voltage applied to the same ground select line during the read operation according to whether the first or second vertical string is the selected vertical string, and

adjust a duration of a pre-charge voltage applied to one of the different bit lines connected to the selected vertical string according to whether the first or second vertical string is the selected vertical string.

14. The nonvolatile memory device of claim II, wherein at least one corresponding vertical string of the plurality of vertical strings comprises:

an upper ground selection transistor connected with one end of a channel of the corresponding vertical string, the ground selection transistor including a gate connected with an upper ground selection line; and

a lower ground selection transistor connected between the upper ground selection transistor and the common source line, the lower ground selection transistor including a gate connected with a lower ground selection line.

18. A nonvolatile memory device comprising:

a memory cell array including a plurality of memory blocks,

each memory block including a first string and a second string extending vertically from a substrate,

a first channel length between the first string and a first common source line, and

a second channel length between the second string and the first common source line,

the second channel length being greater than the first channel length;

a control logic configured to adjust a sensing operation on at least one of the first string and the second string, such that the sensing operation compensates for the second channel length being greater than the first channel length.

19. The nonvolatile memory device of claim 18, wherein the control logic is configured to adjust the sensing operation by:

applying a first read pass voltage to at least one ground selection line of the first string when the first string is accessed; and

applying a second read pass voltage to at least one ground selection line of the second string when the second string is accessed,

the second read pass voltage being higher than the first read pass voltage.

20. The nonvolatile memory device of claim 18, wherein the control logic is configured to adjust the sensing operation by adjusting a develop time of the sensing operation based on whether the first string or second string is accessed.

21. The nonvolatile memory device of claim 18, wherein at least one of the memory blocks includes a merged word line structure.

22. A memory system comprising:

at least one nonvolatile memory device according to claim 18; and

a processor operatively connected to the at least one nonvolatile memory device.