Systems, methods, and apparatus for memory cells with common source lines

• US 8,953,380 B1
• Filed: 06/26/2014
• Issued: 02/10/2015
• Est. Priority Date: 12/02/2013
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Prabhakar, Venkatraman, Hinh, Long, Jin, Bo, Yu, Xiaojun, Kouznetsov, Igor
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/316,615
• Time in Patent Office: 229 Days
• Field of Search: 365/185.18, 365/185.28, 365/185.05
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

Claims

1. A method comprising:

receiving a first voltage at a first transistor, the first transistor being coupled to a second transistor, the first transistor and second transistor being included in a first memory cell;

receiving a second voltage at a third transistor, the third transistor being coupled to a fourth transistor, the third transistor and fourth transistor being included in a second memory cell, the first memory cell and the second memory cell being coupled to a common source line;

receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor; and

receiving a fourth voltage at a gate of the first transistor, the fourth voltage causing, via Fowler-Nordheim tunneling, a change in one or more electrical properties of a charge storage layer included in the first transistor.

2. The method of claim 1 further comprising:

receiving a fifth voltage at a source of the second transistor and a source of the fourth transistor via the common source line, and

wherein the third voltage causes the second transistor and fourth transistor to operate in cutoff mode.

3. The method of claim 2, wherein the fifth voltage is between about −

0.5V and −

5V.

4. The method of claim 1, wherein the first voltage is received at a drain of the first transistor, and wherein the second voltage is received at a drain of the third transistor.

5. The method of claim 4, wherein the first voltage is between about −

0.5V and −

5V, and wherein the second voltage is between about 0.5V and 5V.

6. The method of claim 4, wherein a difference between the first voltage and the fourth voltage is between about 4V and 12V.

7. The method of claim 1, wherein the third voltage is between about −

0.5V and −

5V.

8. The method of claim 1, wherein the first transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor.

9. The method of claim 8, wherein the fourth voltage causes, via Fowler-Nordheim tunneling, a change in one or more electrical properties of a charge storage layer of the SONOS transistor.

10. The method of claim 8, wherein the charge storage layer comprises at least one material selected from the group consisting of:

silicon oxy-nitride, aluminum oxide, hafnium oxide, hafnium aluminum oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide, and lanthanum oxide.

11. A device comprising:

a first transistor configured to receive a first voltage via a first bit line;

a second transistor coupled to the first transistor and a common source line;

a third transistor configured to receive a second voltage via a second bit line; and

a fourth transistor coupled to the third transistor and the common source line,

wherein the first transistor includes a charge storage layer configured to change one or more electrical properties via Fowler-Nordheim tunneling in response to receiving the first voltage and a fourth voltage, the fourth voltage being received at a gate of the first transistor.

12. The device of claim 11, wherein the second transistor and the fourth transistor are configured to operate in a cutoff mode in response to receiving a third voltage during programming of the first transistor, wherein the first transistor and the second transistor are included in a first memory cell, wherein the third transistor and the fourth transistor are included in a second memory cell, wherein the first memory cell is included in a first row and a first column of a memory cell array, and wherein the second memory cell is included in the first row and a second column of the memory cell array.

13. The device of claim 12, wherein the common source line is coupled to all memory cells in the first row of the memory cell array.

14. The device of claim 11, wherein the second transistor and the fourth transistor each have a channel length that is between about 25 nm and 180 nm.

15. The device of claim 11, wherein the first transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor.

16. The device of claim 15, wherein the fourth voltage causes, via Fowler-Nordheim tunneling, a change in one or more electrical properties of a charge storage layer of the SONOS transistor.

17. A system comprising:

voltage control circuitry configured to generate a first voltage, a second voltage, a third voltage, and a fourth voltage;

a memory device coupled to the voltage source, the memory device including at least a first memory cell and a second memory cell coupled to a common source line, the first memory cell including a first transistor coupled to a second transistor, the second memory cell including a third transistor coupled to a fourth transistor, and wherein in response to an initiation of a programming operation, the memory device is configured to;

receive the first voltage at the first transistor;

receive the second voltage at the third transistor;

receive the third voltage at a gate of the second transistor and a gate of the fourth transistor; and

receive the fourth voltage at a gate of the first transistor, the fourth voltage causing, via Fowler-Nordheim tunneling, a change in one or more electrical properties of a charge storage layer included in the first transistor.

18. The system of claim 17, wherein the third voltage causes the second transistor and fourth transistor to operate in cutoff mode, wherein the first memory cell is included in a first row and a first column of the memory device, and wherein the second memory cell is included in the first row and a second column of the memory device.

19. The system of claim 17, wherein the first transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor.

20. The system of claim 19, wherein the fourth voltage causes, via Fowler-Nordheim tunneling, a change in one or more electrical properties of a nitride layer of the SONOS transistor.