Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device

• US 8,954,017 B2
• Filed: 09/28/2011
• Issued: 02/10/2015
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kothari, Love, Hukkoo, Ajat, Thompson, Kerry Alan
• Primary Examiner(s): Milord, Marceau
• Application Number:
  US13/247,295
• Publication Number:
  US 20130045779A1
• Time in Patent Office: 1,231 Days
• Field of Search: 455/76, 455/550.1, 455/552.1, 455/557, 455/414.1, 455/556.1, 455/556.2, 455/63.1, 455/67.13, 455/114.2, 455/260, 455/572
• US Class Current: 455/76
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.

Claims

1. A communications device, comprising:

a clocking module configured to provide a clocking signal;

a phase-locked loop (PLL) configured to multiply the clocking signal by a variable integer value to provide a PLL clock signal;

a power management unit (PMU) configured to receive the PLL clock signal and provide a power signal based on the PLL clock signal; and

a radio frequency (RF) transceiver configured to operate on an information bearing signal using the power signal to provide a transmission communication signal.

2. The communications device of claim 1, further comprising:

a baseband module configured to receive input information, and to provide the input information in the information bearing signal to the RF transceiver.

3. The communications device of claim 2, wherein the baseband module is further configured to provide a channel transmission signal to the PLL to set a value for the variable integer value.

4. The communications device of claim 3, wherein the transmission communication signal is configured to occupy a communication channel from among a plurality of communication channels.

5. The communications device of claim 4, wherein the baseband module is further configured to determine the communication channel that is occupied by the transmission communication signal.

6. The communications device of claim 4, wherein the PLL clock signal includes a fundamental component and one or more harmonics of the fundamental component, the one or more harmonics not occupying the communication channel.

7. The communications device of claim 6, wherein the baseband module is further configured to compare the one or more harmonics of the fundamental component of the PLL clock signal with the communication channel that is occupied by the transmission communication signal.

8. The communications device of claim 7, wherein the baseband module is further configured to cause the PLL to multiply one or more harmonics of the fundamental component for the clocking signal by a second value when at least one of the one or more harmonics of the PLL clock signal occupy the communication channel occupied by the transmission communication signal.

9. The communications device of claim 4, wherein the power signal includes a direct current (DC) component, a fundamental component of the PLL clock signal, and one or more harmonics of the fundamental component, wherein the variable integer value is selected so that the one or more harmonics do not occupy the communication channel.

10. The communications device of claim 9, wherein the DC component provides power for operation of the RF transceiver.

11. The communications device of claim 1, wherein the PLL is configured to multiply the clocking signal by a first integer value to produce a first PLL clock signal having a first fundamental component and one or more harmonics of the first fundamental component.

12. The communications device of claim 11, wherein the PLL is configured to multiply the clocking signal by a second integer value to produce a second PLL clock signal having a second fundamental component and one or more harmonics of the second fundamental component.

13. The communications device of claim 12, wherein the second integer value is chosen such that the one or more harmonics of the second fundamental component do not degrade the transmission communication signal as much as the one or more harmonics of the first fundamental component.

14. The communications device of claim 1, wherein the clocking module is configured to provide a transceiver clocking signal to the RF transceiver.

15. The communications device of claim 1, wherein the PLL is further configured to multiply the clocking signal to provide the PLL signal so that the transmission communication signal is not degraded by one or more harmonics of the PLL clock signal that occupies a communication channel of the transmission communication signal.

16. The communications device of claim 1, wherein the PLL comprises:

a phase-frequency detector configured to output an error signal based on a difference between a feedback signal and the clocking signal;

a voltage controlled oscillator configured to output an intermediate clock signal based on the error signal;

a PLL output divider configured to output a plurality of PLL clock signals based on the intermediate clock signal; and

a frequency divider configured to receive the intermediate clock signal and a channel transmission signal, wherein the feedback signal is generated by the frequency divider by dividing the intermediate clock signal by the variable integer value based on the channel transmission signal to match the clocking signal to the intermediate clock signal.

17. The communications device of claim 16, wherein the frequency divider is configured to adjust the intermediate clock signal by changing the variable integer value from a first integer value to a second integer value that the clocking signal is multiplied by.

18. The communications device of claim 17, wherein the frequency divider is configured to select the variable integer value from a plurality of integer values based on the channel transmission signal.

19. The communications device of claim 17, wherein the frequency divider comprises a plurality of dividers, wherein each divider in the plurality of dividers provides a corresponding PLL clock signal from the plurality of PLL clock signals.

20. The communications device of claim 1, wherein the variable integer value is based on a transmission channel over which the transmission communication signal is to be transmitted.

21. A communications device, comprising:

a clocking module configured to provide a clocking signal;

a phase-locked loop (PLL) configured to multiply the clocking signal by a variable integer value to provide a PLL clock signal;

a power management unit (PMU) configured to provide a power signal based on the PLL clock signal; and

a radio frequency (RF) transceiver configured to operate on an information bearing signal using the power signal to provide a transmission communication signal;

wherein the PLL is further configured to multiply the clocking signal to provide the PLL clock signal so that a communication channel that is occupied by each of one or more harmonics of the PLL clock signal is different from a communication channel that is occupied by the transmission communication signal.

22. A method for reducing noise coupled to a communication signal provided by a cellular phone, the method comprising:

providing a clocking signal;

multiplying, by a phase-locked loop (PLL), the clocking signal by a variable integer value;

providing a PLL clock signal based on the multiplying of the clocking signal by the variable integer value;

receiving the PLL clock signal and providing a power signal based upon the received PLL clock signal;

operating on an information bearing signal using the power signal; and

providing a transmission communication signal based on the power signal.

23. A communications device, comprising:

a phase-locked loop (PLL) configured to generate a PLL clock signal having a fundamental frequency component;

a power management unit (PMU) configured to provide a power signal based on the PLL clock signal, wherein the power signal includes a DC component and one or more harmonics of the fundamental frequency component of the PLL; and

a radio frequency (RF) transceiver, powered by the DC component of the power signal, and configured to operate on an information bearing signal to provide a transmission communication signal;

wherein the PLL is controlled so that the one or more harmonics in the power signal do not occur in a frequency channel occupied by the transmission communication signal.

24. The communications device of claim 23, further comprising:

a baseband module configured to determine the frequency channel occupied by the transmission communication signal and control a divider ratio of the PLL so that the one or more harmonics in the power signal do not occur in the frequency channel occupied by the transmission communication signal.