Method and device to process digital media streams

• US 8,954,174 B2
• Filed: 04/27/2009
• Issued: 02/10/2015
• Est. Priority Date: 08/06/2003
• Status: Active Grant

• Current Assignee: Creative Technology Ltd.
• Original Assignee: Creative Technology Ltd.
• Inventors: Savell, Thomas C.
• Primary Examiner(s): Saunders, Jr., Joseph
• Application Number:
  US12/430,867
• Publication Number:
  US 20090228127A1
• Time in Patent Office: 2,115 Days
• Field of Search: 700/94, 370/258
• US Class Current: 700/94
• CPC Class Codes: H04L 12/43 with synchronous transmission, e.g. time division multiplex [TDM], slotted rings

Abstract

A digital processing circuit for processing media data includes a data path arranged to transmit at least media data along the data path between a plurality of processing modules connected serially. The data is transmitted directly from the output of a first module to an input of a second module of the plurality by sequential clocking signals. A routing controller controls transmission of data from the first of the plurality of processing modules to any target processing module selected from the plurality of modules by providing an identification for the target processing module in a signal provided on the datapath.

Claims

1. A digital processing device configured to process media data, the device comprising:

a data path arranged in a ring configuration to transmit at least media data along the data path between a plurality of processing modules integrated within the digital processing device and connected serially such that data is transmitted directly from the output of a first module to an input of a second module of the plurality of processing modules by sequential clocking signals; and

a routing controller configured to control transmission of data from the first of the plurality of processing modules to any target processing module selected from the plurality of modules by providing an identification for the target processing module in a signal provided on the data path;

wherein each of the processing modules has a fixed output time slot and a variable input time slot allocated to it, the time allocated to the variable time slot determined by the routing controller.

2. The digital processing device as recited in claim 1 wherein the routing controller controls transmission of data from the first of the plurality of processing modules to any target processing module using time division multiplexed addressing.

3. The digital processing device as recited in claim 1 wherein the data path comprises at least one of an audio bus, a transport bus, and a parameter bus.

4. The digital processing device as recited in claim 1 wherein data path includes a parameter bus which transmits data to be used by a respective one of the plurality of modules to define the functionality of the module.

5. The digital processing device as recited in claim 1 wherein repeated processing by a single module of the plurality is effectuated by allowing the output of a source module of the plurality to be fed to the input of the same module thereby equating the source and target modules.

6. The digital processing device as recited in claim 1 wherein the routing controller provides routing along the data path to processing modules using one of chip select, address, write enable, and write data lines.

7. The digital processing device as recited in claim 1, wherein the data path comprises a total number of time-slots for communicating media data at a plurality of different bit rates such that the sum of a number of time-slots allocated to each one of the plurality of bit rates equals the total number of time-slots.

8. The digital processing device as recited in claim 1, wherein parameters associated with different processing modules are offset by a differing number of time slots such that the parameters are provided in time slots that precede the fixed output time slots of the associated processing modules.

9. The digital processing device as recited in claim 1, wherein the plurality of processing modules are selected from the group consisting of:

an audio memory transport module, a delay module, a sample rate converter (SRC) module, a filter module, a mixer module, a digital signal processing (DSP) module, and a digital Input/Output module.

10. The digital processing device as recited in claim 1 wherein the digital processing device is in the form of a chip.

11. A method to process media data with a digital processing device, the method comprising:

transmitting media data along a data path between a plurality of processing modules integrated within the digital processing device and connected serially such that data is transmitted directly from the output of a first module to an input of a second module of the plurality of processing modules by sequential clocking signals; and

controlling transmission of data from the first of the plurality of processing modules to any target processing module selected from the plurality of modules by providing an identification for the target processing module in a signal provided on the data path,

wherein each of the processing modules has a fixed output time slot and a variable input time slot allocated to it.

12. The method as recited in claim 11, wherein controlling transmission of data from the first of the plurality of processing modules to any target processing module comprises:

using time division multiplexed addressing.

13. The method as recited in claim 11, wherein the data path comprises at least one of an audio bus, a parameter bus, and a transport bus.

14. The method as recited in claim 11, wherein the data path includes a parameter bus which transmits data to be used by a respective one of the plurality of modules to define the functionality of the module.

15. The method as recited in claim 11, further comprising:

processing repeatedly by a single module of the plurality by allowing the output of a source module of the plurality to be fed to the input of the same module thereby equating the source and target modules.

16. The method as recited in claim 11, further comprising:

routing along the data path to processing modules using one of chip select, address, write enable, and write data lines.

17. The method as recited in claim 11, wherein the data path comprises a total number of time-slots and wherein transmitting media data comprises:

transmitting media data at a plurality of different bit rates such that the sum of a number of time-slots allocated to each one of the plurality of bit rates equals the total number of time-slots.

18. The method as recited in claim 11, further comprising:

offsetting by a differing number of time slots parameters associated with different processing modules such that the parameters are provided in time slots that precede the fixed output time slots of the associated processing modules.

19. A non-transitory computer-readable medium having computer-executable instructions for performing the steps of:

transmitting media data along a data path between a plurality of processing modules integrated within a digital processing device and connected serially such that data is transmitted directly from the output of a first module to an input of a second module of the plurality of processing modules by sequential clocking signals; and

controlling transmission of data from the first of the plurality of processing modules to any target processing module selected from the plurality of modules by providing an identification for the target processing module in a signal provided on the data path,

wherein each of the processing modules has a fixed output time slot and a variable input time slot allocated to it.

20. The non-transitory computer-readable medium as recited in claim 19, wherein controlling transmission of data from the first of the plurality of processing modules to any target processing module comprises:

using time division multiplexed addressing.

21. The non-transitory computer-readable medium as recited in claim 19, further comprising:

processing repeatedly by a single module of the plurality by allowing the output of a source module of the plurality to be fed to the input of the same module thereby equating the source and target modules.