Memory hub and access method having a sequencer and internal row caching

• US 8,954,687 B2
• Filed: 05/27/2005
• Issued: 02/10/2015
• Est. Priority Date: 08/05/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US11/139,274
• Publication Number:
  US 20050223161A1
• Time in Patent Office: 3,546 Days
• Field of Search: 711/154, 711/118, 711/105, 711/109, 711/5, 709/214, 345/557
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the memory module is not being accessed by the controller, a sequencer in the memory module generates requests to read data from a row of memory cells. The data read responsive to the generated read requests are also stored in the row cache memory. As a result, read data in the row being accessed may be stored in the row cache memory even though the data was not previously read from the memory device responsive to a memory request from the controller.

Claims

1. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface receiving a memory request for access to a row of memory cells in at least one of the memory devices, wherein the memory request includes a read request to read data from a series of memory cells within the row of memory cells and wherein the series of memory cells in the row of memory cells comprises less than all the memory cells in the row of memory cells;

a memory device interface coupled to the memory devices, the memory device interface being operable to couple the memory request to the memory devices in an order different than an order the memory requests are received to access memory cells in the row of memory cells in at least one of the memory devices and to receive read data from the series of memory cells responsive to the read request included in the memory request;

a sequencer coupled to the link interface and the memory device interface, the sequencer configured to keep track of remaining memory cells in the row of memory cells not included in the series of memory cells in the row of memory cells read responsive to the received memory request, the sequencer further being configured to generate memory requests and couple to the memory device interface the generated memory requests to read data from the remaining memory cells in the same row of memory cells being accessed responsive to the memory request being coupled from the memory device interface to the at least one memory device, wherein the remaining memory cells in the same row of memory cells excludes the series of memory cells in the row of memory cells accessed responsive to the memory request, the sequencer being operable to generate and couple to the memory device the generated memory requests to read data only when memory requests are not being transferred from the link interface to the memory device interface, the read data read from the other memory cells in the same row of memory cells being accessed being stored in a row cache memory; and

the row cache memory coupled to the memory device interface and the sequencer configured to receive and store the read data from the remaining memory cells in the same row of memory cells being accessed responsive to the generated memory requests.

2. The memory module of claim 1 wherein the memory device interface further comprises a first-in, first-out buffer that is operable to receive and to store memory requests received from the link interface and from the sequencer and to transfer the stored memory requests to the at least one memory device in the order in which they were received.

3. The memory module of claim 1 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

4. The memory module of claim 3 wherein the memory device interface further comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface and from the sequencer and to transfer the stored memory requests to the at least one memory device in the order in which they were received.

5. The memory module of claim 1 wherein the link interface comprises an optical input/output port.

6. The memory module of claim 1 wherein the memory devices comprises dynamic random access memory devices.

7. The memory module of claim 1 wherein the sequencer is operable to output an address contained in each read memory request received from the link interface, and wherein the row cache memory is operable to receive the addresses from the sequencer to determine if data called for by the memory request is stored in the row cache memory, the row cache memory outputting the read data and generating a hit signal if the data called for by the memory request is stored in the row cache memory and generating a row miss signal if the data called for by the memory request is not stored in the row cache memory.

8. The memory module of claim 7 further comprising a multiplexer having data inputs coupled to the row cache memory and to the memory device interface, a data output coupled to the link interface and a control input coupled to receive the row cache hit and row cache miss signals from the row cache memory, the multiplexer coupling read data from the memory device interface responsive to the row cache miss signal and coupling read data from the row cache memory responsive to the row cache hit signal.

9. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface receiving memory requests, wherein each memory request is for access to a series of memory cells in a row of memory cells in at least one of the memory devices and the series of memory cells in a row of memory cells is less than all the memory cells in that row of memory cells;

a memory device interface coupled to the memory devices, the memory device interface configured to re-order how the memory requests are applied to the plurality of memory devices and further configured to couple each re-ordered memory request to the memory devices for access to a respective series of memory cells in a row of memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests, at least some of the memory requests coupled to the memory devices being responsive to memory requests transferred from the link interface to the memory device interface, wherein the memory device interface re-orders the memory requests to apply read requests before write requests;

a sequencer coupled to the link interface and the memory device interface and the row cache memory, the sequencer being operable to convert memory request received by the link interface into memory device memory requests provided to the memory device interface, the format of the memory device memory requests different than memory requests received by the link interface, the sequencer being operable to output an address contained in each read memory request received from the link interface, the sequencer further being operable to output an address other than an address contained in a read memory request received from the link interface, wherein the address other than the address contained in the read memory request received from the link interface includes an address for other memory cells in the row of memory cells not accessed by the address contained in the read memory request;

a row cache memory coupled to the memory device interface for receiving and storing read data from the other memory cells in the row of memory cells responsive to the address other than the address contained in one of the memory read requests being coupled from the memory device interface to the at least one memory device, device, the row cache memory further being operable to receive the addresses from the sequencer to determine if data called for by the memory request is stored in the row cache memory, the row cache memory outputting the read data and generating a hit signal if the data called for by the memory request is stored in the row cache memory and generating a row miss signal if the data called for by the memory request is not stored in the row cache memory; and

a multiplexer having data inputs coupled to the row cache memory and to the memory device interface, a data output coupled to the link interface and a control input coupled to receive the row cache hit and row cache miss signals from the row cache memory, the multiplexer coupling read data from the memory device interface responsive to the row cache miss signal and coupling read data from the row cache memory responsive to the row cache hit signal.

10. The memory module of claim 9 wherein the memory device interface further comprises a buffer that is operable to receive and store memory requests from the link interface and from the sequencer.

11. The memory module of claim 9 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

12. The memory module of claim 11 wherein the memory device interface further comprises a buffer that is operable to receive and store memory requests received from the link interface and from the sequencer.

13. The memory module of claim 9 wherein the link interface comprises an optical input/output port.

14. The memory module of claim 9 wherein the memory devices comprises dynamic random access memory devices.

15. A memory hub, comprising:

a link interface receiving memory requests, at least some of the memory requests including an address for a series of memory cells in a row of memory cells, wherein the series of memory cells in the row of memory cells is less than all of the memory cells in the row of memory cells;

a memory device interface operable to re-order formatted memory requests and apply the re-ordered formatted memory requests to the memory devices and to receive read data responsive to at least some of the formatted memory requests, at least some of the formatted memory requests output by the memory device interface being responsive to memory requests transferred from the link interface to the memory device interface;

a row cache memory coupled to the memory device interface for receiving and storing read data received from the memory device interface based on at least one of the formatted memory requests being output from the memory device interface; and

a sequencer coupled to the link interface and the memory device interface and the row cache memory, the sequencer being operable to format memory requests received by the link interface into a different format to provide formatted memory requests to the memory device interface generated memory requests to read data from memory cells in the row of memory cells not included in a respective received memory request, the sequencer being operable to generate and couple to the memory device interface the generated memory requests to read data when memory requests are not being transferred from the link interface, the read data read responsive to the generated memory requests from the sequencer being stored in the row cache memory.

16. The memory hub of claim 15 wherein the memory device interface further comprises a buffer that is operable to receive and store memory requests received from the link interface and from the sequencer.

17. The memory hub of claim 15 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

18. The memory hub of claim 17 wherein the memory device interface further comprises a buffer that is operable to receive and store memory requests received from the link interface and from the sequencer.

19. The memory hub of claim 15 wherein the link interface comprises an optical input/output port.

20. The memory hub of claim 15 wherein the sequencer is operable to output an address contained in each read memory request received from the link interface, and wherein the row cache memory is operable to receive the addresses from the sequencer to determine if data called for by the memory request is stored in the row cache memory, the row cache memory outputting the read data and generating a hit signal if the data called for by the memory request is stored in the row cache memory and generating a row miss signal if the data called for by the memory request is not stored in the row cache memory.

21. The memory hub of claim 20 further comprising a multiplexer having data inputs coupled to the row cache memory and to the memory device interface, a data output coupled to the link interface and a control input coupled to receive the row cache hit and row cache miss signals from the row cache memory, the multiplexer coupling read data from the memory device interface responsive to the row cache miss signal and coupling read data from the row cache memory responsive to the row cache hit signal.

22. A method of reading data in each of a plurality of memory modules using a controller coupled to the memory modules, the method comprising:

receiving, by a memory hub, memory requests from the controller by a first one of the memory modules, at least one of the memory requests being a request to access a series of memory cells in a row of memory cells of at least one memory device in a plurality of memory devices included in the first memory module, wherein the series of memory cells in the row of memory cells includes less than all of the memory cells in the row of memory cells;

re-ordering, by a memory device interface in the memory hub, the received memory requests;

coupling, by the memory hub, re-ordered memory requests to the at least one memory device in the first memory module;

generating, by a sequencer in the memory hub, requests to read data from other memory cells in the same row of memory cells accessed responsive to the at least one of the memory requests being a request to access the series of memory cells in the row of memory cells of the at least one memory device, the requests being generated when memory requests from the controller are not being coupled to the at least one memory device;

re-ordering, by a memory device interface in the memory hub, the received and generated memory requests;

coupling, by the memory hub, the generated memory requests to the at least one memory device; and

storing in cache memory in the first memory module read data responsive to the generated memory requests.

23. The method of claim 22, further comprising, in response to a memory request from the controller to read data from the first memory module:

determining if the read data are stored in the cache memory;

if the read data are stored in the cache memory, transferring the requested read data from the cache memory to the controller; and

if the read data are not stored in the cache memory, transferring the requested read data from the at least one memory device to the controller.

24. The method of claim 22 wherein the act of receiving memory requests from the controller by a first one of the memory modules comprises receiving optical signals corresponding to the received memory requests.

25. The method of claim 22 wherein the memory devices included in the first memory module comprises dynamic random access memory devices.