Switching optically connected memory

• US 8,954,698 B2
• Filed: 04/13/2012
• Issued: 02/10/2015
• Est. Priority Date: 04/13/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schenfeld, Eugen, Chakraborty, Abhirup
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): VO, THANH DUC
• Application Number:
  US13/446,931
• Publication Number:
  US 20130275703A1
• Time in Patent Office: 1,033 Days
• US Class Current: 711/165
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/50 Control mechanisms for virtual memory, cache or TLB
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/683 Invalidation
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]

Abstract

Memory is dynamically switched through the optical-switching fabric using at least one communication pattern to transfer memory space in the memory blades from one processor to an alternative processor in the processor blades without physically copying data in the memory to the processors. Various communication patterns for the dynamically switching are supported.

Claims

1. An optically-connected memory (OCM) system, comprising:

at least one processor blade;

at least one memory blade, remotely separated from the at least one processor blade;

at least one processor device arranged in one of the at least one processor blade and the at least one memory blade;

at least one memory in the at least one memory blade; and

an optical switching fabric communicatively coupled between the at least one processor blade and the at least one memory blade;

wherein the optical switching fabric is configured for;

dynamically switching the at least one memory using a selected one of a plurality of available communication patterns to transfer a memory space in the at least one memory blade from the at least one processor device to an alternative one of the at least one processor device in the at least one processor blade without physically copying data in the at least one memory to the at least one processor device, wherein the dynamically switching further includes;

allocating memory from one of the at least one memory blade upon receiving memory request from the one of the plurality of processors, wherein a circuit is established with the memory for the one of the plurality of processors, an address space of the memory sent to the one of the plurality of processors,

mapping the address space of the memory to a system memory address (SMA) space upon the one of the plurality of processors receiving the address space of the memory, wherein entries of the page table corresponding to the address space are created,

retaining a remote memory superpage of the memory in the memory blade when reading the remote memory super page of the memory into the one of the plurality of processors, and

transferring a physical memory address space from the one of the processors to the alternative one of the plurality of processors.

2. The system of claim 1, wherein the at least one memory retains the data in the at least one memory while sending meta data to the at least one processor device for regenerating mapping tables and page tables on the at least one processor blade with information included in the meta data.

3. The system of claim 1, further including:

a plurality of optical external links for optimizing a point-to-point connection within the optical switching fabric,

at least one optical circuit switch communicatively connected to the plurality of optical external links, and

at least one independent circuit established between the at least one processor device and at least one memory blade sharing the at least one optical circuit switch;

wherein access to the at least one memory in the at least one memory blade is allowed through the at least one independent circuit.

4. The system of claim 3, wherein the optical switching fabric disconnects one of the at least one independent circuit to one of the at least one memory blade while signaling another one of the at least one memory blade to establish an alternative one of the at least one independent circuit with the another one of the at least one memory blade.

5. The system of claim 1, further including a plurality of channels within the optical switching fabric for providing access to the at least one memory.

6. The system of claim 5, wherein the optical switching fabric shares the at least one memory in the at least one memory blade between more than one of the at least one processor device by occupying a non-overlapping portion of the at least one memory.

7. The system of claim 2, wherein the at least one processor device performs at least one of:

sending the metadata and a switching request to at least one of the at least one processor device,

adjusting a remote machine memory address (RMMA) space and flushing a translation look-aside buffer (TLB),

performing an unmapping operation for removing entries in page tables that map a linear address to the RMMA space,

grafting the RMMA space onto an available system memory address (SMA) space of the at least one of the processor device and regenerating the mapping tables, and

dynamically switching the at least one memory from an active node of the at least one of the processor device to a remote active node of the alternative one of the at least one processor device.

8. The system of claim 1, wherein the at least one processor device uses page tables by one of the processor device for instantaneous access to the data.

9. In an optically-connected memory (OCM) system having a plurality of processors arranged in processor blades and memory in memory blades, with each of the processor blades and the memory blades organized in racks communicatively coupled through an optical-switching fabric, the processor blades and the memory blades remotely separated, a computer program product in a computing environment using a processor device, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising:

a first executable portion for dynamically switching the memory through the optical-switching fabric using a selected one of a plurality of available communication patterns to transfer a memory space in the memory blades from one of the plurality of processors to an alternative one of the plurality of processors in the processor blades without physically copying data in the memory to the plurality of processors, wherein the dynamically switching further includes;

allocating memory from one of the memory blades upon receiving a memory request from the one of the plurality of processors, wherein a circuit is established with the memory for the one of the plurality of processors, an address space of the memory sent to the one of the plurality of processors,

mapping the address space of the memory to a system memory address (SMA) space upon the one of the plurality of processors receiving the address space of the memory, wherein entries of the page table corresponding to the address space are created,

retaining a remote memory superpage of the memory in the memory blade when reading the remote memory super page of the memory into the one of the plurality of processors, and

transferring a physical memory address space from the one of the processors to the alternative one of the plurality of processors.

10. The computer program product of claim 9, further including a second executable portion for retaining the data in the memory while sending meta data to the processors for regenerating mapping tables and page tables on the processor blades with information included in the meta data.

11. The computer program product of claim 9, wherein the memory blades are communicatively coupled with the plurality of processors in the optical-switching fabric via an optical circuit network comprising a plurality of optical external links and at least one optical circuit switch, and further including a second executable portion for allowing access of the plurality of processors to the memory in the memory blades through at least one independent circuit established between the processor blades and the memory blades within the optical circuit network.

12. The computer program product of claim 9, wherein the processor blades and the memory blades are configured with a plurality of channels, and further including a second executable portion for accessing the memory through the plurality of channels.

13. The computer program product of claim 12, further including a third executable portion for sharing the memory in the memory blades between more than one of the plurality of processors by occupying a non-overlapping portion of the memory.

14. The computer program product of claim 9, further including a second executable portion for disconnecting down a circuit to one of the memory blades while signaling another one of the memory blades to establish a circuit with the another one of the memory blades.

15. The computer program product of claim 10, further including a second executable portion for performing at least one of:

sending the meta data and a switching request to the one of the plurality of processors,

adjusting a remote machine memory address (RMMA) space and flushing a translation look-aside buffer (TLB),

performing an unmapping operation for removing entries in the page tables that map a linear address to the RMMA space,

grafting the RMMA space onto an available system memory address (SMA) space of the one of the plurality of processors and regenerating the mapping tables, and

dynamically switching the memory from an active node of the one of the plurality of processors to a remote active node of the alternative one of the plurality of processors.

16. The computer program product of claim 9, further including a second executable portion for using the page tables by one of the plurality of processors for instantaneous access to the data.