Controlling temperature of multiple domains of a multi-domain processor using a cross domain margin

• US 8,954,770 B2
• Filed: 09/28/2011
• Issued: 02/10/2015
• Est. Priority Date: 09/28/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishan, Avinash N., Ziv, Tomer, Rajwan, Doron, Rotem, Efraim
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Chan, Danny
• Application Number:
  US13/247,580
• Publication Number:
  US 20130080804A1
• Time in Patent Office: 1,231 Days
• Field of Search: 713/320
• US Class Current: 713/320
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a first domain located on a die and including at least one core to execute instructions;

a second domain located on the die and including at least one functional unit to execute a specialized function, wherein the first and second domains can operate at independent frequencies; and

a power control unit (PCU) coupled to the first and second domains, the PCU including a thermal logic to cause a reduction in a frequency of the first domain by a frequency bin of the processor based on a value of a counter for the first domain in response to a temperature of the second domain exceeding a sum of a throttle threshold for the second domain and a cross-domain margin, wherein the thermal logic is, for each of a plurality of iterations, to update the counter value for the first domain when the second domain temperature is determined to exceed the sum, wherein the cross-domain margin is a programmable temperature margin parameter stored in a configuration non-volatile storage of the processor accessible to the thermal logic and corresponds to a marginal level above the throttle threshold for the second domain at which a power consumption of the first domain is to be reduced to allow the temperature of the second domain to be reduced, the frequency bin corresponding to a smallest multiple by which the first domain frequency can change.

2. The processor of claim 1, wherein the thermal logic is to cause the first domain frequency to be reduced by the frequency bin of the processor when the counter value is equal to N, wherein N is a programmable parameter.

3. The processor of claim 1, wherein the thermal logic is, for each of a plurality of iterations, to update a value of a counter for the first domain when a temperature of the first domain is determined to exceed a throttle threshold for the first domain.

4. The processor of claim 2, where N is controllable by a user.

5. The processor of claim 1, wherein the thermal logic is to cause the reduction in the first domain frequency if a temperature of the first domain is greater than a throttle threshold for the first domain.

6. The processor of claim 1, wherein the thermal logic is to cause a reduction in a frequency of the second domain in response to a temperature of the first domain exceeding a sum of a throttle threshold for the first domain and the cross-domain margin.

7. The processor of claim 1, wherein the processor includes the configuration non-volatile storage to store the throttle threshold and the cross-domain margin, wherein the throttle threshold is of a different value than a junction temperature of the processor.

14. The processor of claim 2, wherein the thermal logic is, for each of a plurality of iterations, to update the value of the counter for the first domain when a temperature of the first domain is determined to exceed a throttle threshold for the first domain, and to cause the reduction in the first domain frequency by the frequency bin of the processor when the counter value is equal to X, wherein X and N are different values to be stored in a storage of the processor.

8. A method comprising:

determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold for the second domain and a cross-domain margin, wherein the cross-domain margin is a programmable temperature margin parameter stored in a non-volatile storage of the multi-domain processor and corresponds to a marginal level above the throttle threshold for the second domain at which a power consumption of a first domain of the multi-domain processor is to be reduced to allow the temperature of the second domain to be reduced;

updating a value of a counter for the first domain when the second domain temperature is determined to exceed the sum, and updating the counter value when the first domain is determined to exceed a throttle threshold for the first domain; and

reducing a frequency of the first domain by a frequency bin of the first domain when the counter value equals N, otherwise maintaining a current frequency of the first domain.

9. The method of claim 8, further comprising reducing the first domain frequency if a temperature of the first domain is greater than a throttle threshold for the first domain.

10. The method of claim 8, further comprising:

determining whether a temperature of the first domain is greater than the sum of a throttle threshold for the first domain and the cross-domain margin; and

if so, reducing a frequency of the second domain by a second selected amount, otherwise maintaining a current frequency of the second domain.

11. A system comprising:

a multi-domain processor including a core domain having a plurality of cores, a non-core domain including at least one processing engine, and a system agent domain including a power controller, wherein the power controller is to reduce a frequency of the core domain by a selected amount when a temperature of the non-core domain is greater than a sum of a throttle threshold and a cross-domain margin for the non-core domain, wherein the cross-domain margin is a programmable temperature margin parameter stored in a non-volatile storage of the multi-domain processor and corresponds to a marginal level above the throttle threshold for the non-core domain at which a power consumption of the core domain is to be reduced to allow the temperature of the non-core domain to be reduced, and otherwise to maintain a current frequency of the core domain, wherein the power controller is to update a value of a counter for the core domain when the non-core domain temperature is determined to exceed the sum, and to reduce the core domain frequency by a bin frequency when the counter value equals N, the frequency bin corresponding to a smallest multiple by which the core domain frequency can change.

12. The system of claim 11, wherein the power controller is to reduce the frequency of the core domain after a plurality of iterations in which it is determined that the non-core domain temperature is greater than the sum.

13. The system of claim 11, wherein the power controller is to reduce the frequency of the core domain after a plurality of iterations in which it is determined that the non-core domain temperature is greater than the throttle threshold for the non-core domain.