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Veryifing low power functionality through RTL transformation

  • US 8,954,904 B1
  • Filed: 04/30/2013
  • Issued: 02/10/2015
  • Est. Priority Date: 04/30/2013
  • Status: Active Grant
First Claim
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1. A computer-implemented method for power aware sequential equivalence checking, the method comprising:

  • receiving a first register transfer level (RTL) circuit model of a circuit design;

    receiving a first power intent description of the circuit design;

    generating a second RTL circuit model by modifying the first RTL circuit model based on the first power intent description;

    receiving a third RTL circuit model of the circuit design;

    receiving a second power intent description of the circuit design;

    generating a fourth RTL circuit model by modifying the third RTL circuit model based on the second power intent description; and

    performing, by a computer, power aware sequential equivalence checking on the second RTL circuit model and fourth RTL circuit model by verifying that a set of outputs of the second RTL circuit model and fourth RTL circuit model behave the same during a power on state of one or more power domains corresponding to the outputs while excluding behavior of the outputs during a power off state of the one or more power domains corresponding to the outputs.

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