Method of making a compliant printed circuit peripheral lead semiconductor package

• US 8,955,216 B2
• Filed: 05/25/2010
• Issued: 02/17/2015
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: HSIO Technologies LLC
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Nguyen, Donghai D
• Application Number:
  US13/318,181
• Publication Number:
  US 20120044659A1
• Time in Patent Office: 1,729 Days
• Field of Search: 29830-834, 298/46, 298/47, 298/52, 298/41, 174/256, 174/260, 257/679, 361/776, 361/783, 438/464, 438/127
• US Class Current: 29/841
• CPC Class Codes: H01L 21/4867 Applying pastes or inks, e.g. screen printing H01L21/486 takes precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 3/4664 : Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

A compliant printed circuit semiconductor package including a compliant printed circuit with at least a first dielectric layer selectively printed on a substrate with first recesses. A conductive material is printed in the first recesses to form contact members accessible along a first surface of the compliant printed circuit. At least one semiconductor device is located proximate the first surface of the compliant printed circuit. Wirebonds electrically couple terminals on the semiconductor device to the contact members. Overmolding material seals the semiconductor device and the wirebonds to the first surface of the compliant printed circuit. Contact pads on a second surface of the compliant printed circuit are electrically coupled to the contact members.

Claims

1. A method of making a compliant printed circuit semiconductor package comprising the steps of:

selectively printing at least a first dielectric layer on a substrate to create a plurality of first recesses;

metalizing the first recesses to form contact members accessible along a first surface of a compliant printed circuit and contact pads accessible along a second surface, where the contact members are electrically coupled to the contact pads;

locating a plurality of semiconductor devices proximate the first surface of the compliant printed circuit;

forming a plurality of dielectric layers on the first dielectric layer;

forming a circuit geometry in at least one of the plurality of dielectric layers to include at least one intra-die circuit path

wirebonding terminals on the semiconductor devices to the contact members; and

overmolding the semiconductor devices and the wirebonds to the first surface of the compliant printed circuit.

2. The method of claim 1 comprising the steps of:

selectively printing a plurality of dielectric layers on the first dielectric layer to create a plurality of second recesses corresponding to a target circuit geometry; and

plating conductive material in at least a portion of the second recesses comprising circuit geometry electrically coupling the contact members with the contact pads.

3. The method of claim 2 wherein conductive traces in the circuit geometry comprise substantially rectangular cross-sectional shapes.

4. The method of claim 2 comprising locating a conductive material, a non-conductive material, and a semi-conductive material on a single layer.

5. The method of claim 2 comprising the steps of:

locating pre-formed conductive trace materials in the second recesses; and

plating the second recesses to form conductive traces with substantially rectangular cross-sectional shapes.

6. The method of claim 2 comprising the steps of:

pressing a conductive foil into at least a portion of the second recesses;

shearing the conductive foil along edges of the second recesses;

removing excess conductive foil not located in the second recesses; and

plating the second recesses to form conductive traces with substantially rectangular cross-sectional shapes.

7. The method of claim 2 comprising plating a conductive material on one or more of the contact members and the circuit geometry.

8. The method of claim 1 comprising printing a compliant material in a location between the first dielectric layer and at least one of the contact pads.

9. The method of claim 1 comprising:

printing at least one electrical device on a dielectric layer; and

electrically coupling the electrical device to at least one contact member.

10. The method of claim 1 comprising configuring at least one of the contact pads to extend above the compliant printed circuit.

11. The method of claim 1 comprising the steps of:

locating a plurality of semiconductor devices proximate the first surface of the compliant printed circuit; and

wirebonding terminals on the semiconductor devices to the contact members on the compliant printed circuit.

12. A method of making an electrical assembly comprising the steps of:

making the semiconductor package according to the method of claim 1; and

electrically coupling a circuit member with a plurality of the contact pads on the second surface of the compliant printed circuit.

13. The method of claim 12 wherein the circuit member is selected from one of a dielectric layer, a printed circuit board, a flexible circuit, a bare die device, an integrated circuit device, organic or inorganic substrates, or a rigid circuit.