Metalorganic chemical vapor deposition (MOCVD) growth of high performance non-polar III-nitride optical devices

• US 8,956,896 B2
• Filed: 04/05/2012
• Issued: 02/17/2015
• Est. Priority Date: 12/11/2006
• Status: Active Grant

• Current Assignee: Japan Science & Technology Trading Co. Limited, Regents of the University of California (University of California)
• Original Assignee: Japan Science & Technology Trading Co. Limited, Regents of the University of California (University of California)
• Inventors: Schmidt, Mathew C., Kim, Kwang Choong, Sato, Hitoshi, DenBaars, Steven P., Speck, James S., Nakamura, Shuji
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US13/440,087
• Publication Number:
  US 20120199809A1
• Time in Patent Office: 1,048 Days
• Field of Search: 257/102, 257/103, 257/E21.108, 257/E21.132
• US Class Current: 438/29
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01S 2304/04 MOCVD or MOVPE
• CPC Class Codes: H01S 5/34333 with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A method of device growth and p-contact processing that produces improved performance for non-polar III-nitride light emitting diodes and laser diodes. Key components using a low defect density substrate or template, thick quantum wells, a low temperature p-type III-nitride growth technique, and a transparent conducting oxide for the electrodes.

Claims

1. A method for fabricating a III-nitride optoelectronic device, comprising:

(a) growing a III-nitride Light Emitting Diode (LED) or Laser Diode (LD) structure on or above a non-polar or semi-polar plane of a III-nitride substrate or template;

wherein;

the LED or LD structure comprises one or more p-type III-nitride layers, an n-type III-nitride layer, and a non-polar or semi-polar III-nitride active region between the p-type III-nitride layers and the n-type III-nitride layer,

growing the active region includes growing one or more non-polar or semi-polar III-nitride quantum wells and quantum well barriers for the quantum wells,

the quantum wells have one or more well thicknesses and are grown at one or more well growth temperatures,

the quantum well barriers have one or more barrier thicknesses and are grown at one or more barrier growth temperatures, and

the p-type III-nitride layers have one or more thicknesses grown at one or more temperatures and doped with one or more p-type dopant levels; and

(b) fabricating contacts to the LED or LD structure;

wherein the fabricating, including steps (a)-(b), fabricates the device having an external quantum efficiency (EQE) of at least 35% and an output power of at least 25 milliwatts (mW).

2. The method of claim 1, wherein the III-nitride substrate or template is a bulk III-nitride substrate or template grown by an ammonothermal method or by hydride vapor phase epitaxy (HVPE).

3. The method of claim 1, wherein the III-nitride substrate or template is a non-polar sidewall lateral epitaxial overgrowth (SLEO) substrate or template grown by metalorganic chemical vapor deposition (MOCVD) or by hydride vapor phase epitaxy (HVPE).

4. The method of claim 1, wherein the well growth temperatures are in a range from approximately 845°

C. to 890°

C.

5. The method of claim 1, wherein the one or more barrier thicknesses are in a range from approximately 10 to 18 nanometers.

6. The method of claim 1, wherein the one or more barrier growth temperatures are in a range from approximately 915°

C. to 940°

C.

7. The method of claim 1, wherein p-type III-nitride layers in the LED or LD structure are grown at the one or more temperatures less than 150°

C. more than the one or more well growth temperatures.

8. The method of claim 1, wherein the p-type III-nitride layer in the LED or LD structure is grown at the barrier growth temperatures.

9. The method of claim 1, wherein fabricating the contacts includes depositing transparent electrodes on the device having one or more thicknesses.

10. The method of claim 9, wherein one or more of the electrodes are comprised of indium-tin-oxide (ITO).

11. An optoelectronic device fabricated using the method of claim 1.

12. The method of claim 1, wherein the optoelectronic device is a Light Emitting Diode (LED) having the external quantum efficiency (EQE) of at least 35% and the output power of at least 25 mW at a drive current of 20 milliamps (mA).

13. The method of claim 1, wherein the well thicknesses are in a range of approximately 8 to 12 nanometers.

14. The method of claim 1, wherein the non-polar quantum wells are non-polar m-plane quantum wells, the substrate is bulk Gallium Nitride, and the non-polar plane is an m-plane.

15. The method of claim 1, further comprising obtaining the III-nitride substrate or template including a Gallium Nitride substrate or template having a defect density, including stacking fault density, sufficiently low to obtain the external quantum efficiency (EQE) of at least 35% and the output power of at least 25 milliwatts (mW).

16. The method of claim 1, wherein the active region has a thickness of at least 8 nanometers.

17. The method of claim 1, wherein the active region has a thickness in a range of more than 22.5 nm and up to 198 nm.

18. The method of claim 1, wherein the well thicknesses are in a range from greater than 2.5 nanometers up to 12 nanometers.

19. The method of claim 1, wherein the device is an LED and the EQE is in a range of 35-41.4%.

20. The method of claim 19, wherein the output power of at least 25 milliwatts is 25 milliwatts.

21. The method of claim 1, further comprising:

growing the LED structure using Metal Organic Chemical Vapor Deposition, wherein;

the non-polar plane is an m-plane of a Gallium Nitride (GaN) substrate,

the n-type III-nitride layer comprises GaN,

the one or more quantum wells comprise InGaN and have the well thicknesses in a range of 8-12 nanometers (nm),

the quantum well barriers comprise Gallium and Nitrogen and have the barrier thicknesses in a range of 10-18 nm;

the p-type III-nitride layers comprise p-type GaN layers grown using multiple temperature stages and having different thicknesses, wherein the temperatures are less than 150°

C. more than the one or more well growth temperatures;

growing an AlGaN electron blocking layer on the quantum well barrier, wherein an Al composition in the AlGaN electron blocking layer is in a range of 12 to 20%;

depositing the contacts comprising a contact to one or more of the p-type GaN layers and a contact to the n-type GaN, wherein the contacts comprise Indium Tin Oxide (ITO) and/or Zinc Oxide; and

annealing the contacts.

22. The method of claim 21, wherein the contacts have a thickness in a range of 150-350 nm.

23. The method of claim 21, wherein the multiple temperature stages include:

a first stage, wherein a first p-type GaN layer is grown at a first temperature to a first thickness and is doped with a first Magnesium doping level,

a second stage, wherein a second p-type GaN layer is grown on the first p-type GaN layer at a second temperature higher than the first temperature, to a second thickness thicker than the first thickness, and is doped with a second Magnesium doping level lower than the first Magnesium doping level, and

a third stage, wherein a third p-type GaN layer is grown on the second p-type GaN layer at a third temperature higher than the first temperature, to a third thickness thinner than the second thickness, and is doped with a third Magnesium doping level higher than the second Magnesium doping level.

24. The method of claim 1, further comprising controlling the well growth temperatures and/or Trimethylindium flow rate during growth of the quantum wells to obtain an Indium composition in the quantum wells wherein the LED emits with a peak emission in an ultraviolet wavelength range.

25. The method of claim 9, wherein one or more of the contacts include Zinc Oxide.

26. The method of claim 9, wherein the transparent electrodes include a first transparent conducting oxide electrode on the n-type III-nitride layer and a second transparent conducting oxide electrode on the p-type III-nitride layer.