Method for manufacturing semiconductor device

• US 8,956,929 B2
• Filed: 11/15/2012
• Issued: 02/17/2015
• Est. Priority Date: 11/30/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi, Sasagawa, Shinya, Egi, Yuji
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US13/677,663
• Publication Number:
  US 20130137213A1
• Time in Patent Office: 824 Days
• Field of Search: None
• US Class Current: 438/151
• CPC Class Codes: H01L 21/0206 during, before or after processing of insulating layers
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/4757 After-treatment
• CPC Class Codes: H01L 21/47635 After-treatment of these layers
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming an oxide semiconductor layer over an insulating surface;

etching a part of the oxide semiconductor layer so that an island-shaped oxide semiconductor layer is formed;

cleaning a top surface and a side surface of the island-shaped oxide semiconductor layer; and

forming a source electrode layer and a drain electrode layer over the island-shaped oxide semiconductor layer after the cleaning step;

further comprising the steps of;

forming an oxide insulating layer having the insulating surface;

forming a gate insulating layer over the island-shaped oxide semiconductor layer after the cleaning step;

forming a gate electrode layer over the gate insulating layer;

forming an insulating layer over the gate electrode layer to overlap with the gate electrode layer;

introducing a dopant into a part of the island-shaped oxide semiconductor layer with use of the gate electrode layer and the insulating layer as a mask;

forming a sidewall insulating layer over the gate insulating layer to cover a side surface of the gate electrode layer and a side surface of the insulating layer;

forming a conductive layer over the island-shaped oxide semiconductor layer, the gate insulating layer, the gate electrode layer, the insulating layer, and the sidewall insulating layer;

forming an interlayer insulating layer over the conductive layer; and

removing a part of the interlayer insulating layer and a part of the conductive layer with a chemical mechanical polishing method until the insulating layer over the gate electrode layer is exposed, thereby forming the source electrode layer and the drain electrode layer.

2. The method according to claim 1, wherein the cleaning step is performed with use of an acid solution.

3. The method according to claim 1, further comprising the step of introducing oxygen into the oxide insulating layer.

4. The method according to claim 1, further comprising the step of introducing oxygen into the oxide semiconductor layer.

5. The method according to claim 1, further comprising the step of forming a layer containing aluminum oxide over the insulating layer, the source electrode layer, the drain electrode layer, the sidewall insulating layer, and the interlayer insulating layer.

6. The method according to claim 1, wherein the etching is a dry etching.

7. A method for manufacturing a semiconductor device comprising the steps of:

forming an oxide semiconductor layer over an insulating surface;

etching a part of the oxide semiconductor layer so that an island-shaped oxide semiconductor layer is formed;

cleaning a top surface and a side surface of the island-shaped oxide semiconductor layer with use of a solution containing diluted hydrofluoric acid; and

forming a source electrode layer and a drain electrode layer over the island-shaped oxide semiconductor layer after the cleaning step;

further comprising the steps of;

forming an oxide insulating layer having the insulating surface;

forming a gate insulating layer over the island-shaped oxide semiconductor layer after the cleaning step;

forming a gate electrode layer over the gate insulating layer;

forming an insulating layer over the gate electrode layer to overlap with the gate electrode layer;

introducing a dopant into a part of the island-shaped oxide semiconductor layer with use of the gate electrode layer and the insulating layer as a mask;

forming a sidewall insulating layer over the gate insulating layer to cover a side surface of the gate electrode layer and a side surface of the insulating layer;

forming a conductive layer over the island-shaped oxide semiconductor layer, the gate insulating layer, the gate electrode layer, the insulating layer, and the sidewall insulating layer;

forming an interlayer insulating layer over the conductive layer; and

removing a part of the interlayer insulating layer and a part of the conductive layer with a chemical mechanical polishing method until the insulating layer over the gate electrode layer is exposed, thereby forming the source electrode layer and the drain electrode layer.

8. The method according to claim 7, further comprising the step of introducing oxygen into the oxide insulating layer.

9. The method according to claim 7, further comprising the step of introducing oxygen into the oxide semiconductor layer.

10. The method according to claim 7, further comprising the step of forming a layer containing aluminum oxide over the insulating layer, the source electrode layer, the drain electrode layer, the sidewall insulating layer, and the interlayer insulating layer.

11. The method according to claim 7, wherein the etching is a dry etching.

12. The method according to claim 11, wherein a concentration of the diluted hydrofluoric acid is 0.5 wt % to 5×

10<sup>−

4</sup> wt %.

13. The method according to claim 11,

wherein the oxide semiconductor layer contains indium, gallium and zinc, and

wherein a concentration of the diluted hydrofluoric acid is 5×

10<sup>−

2</sup> wt % to 5×

10<sup>−

4</sup> wt %.

14. A method for manufacturing a semiconductor device comprising the steps of:

forming an oxide semiconductor layer over an insulating surface;

etching a part of the oxide semiconductor layer so that an island-shaped oxide semiconductor layer is formed;

cleaning a top surface and a side surface of the island-shaped oxide semiconductor layer with use of a solution containing oxalic acid; and

forming a source electrode layer and a drain electrode layer over the island-shaped oxide semiconductor layer after the cleaning step;

comprising the steps of;

forming an oxide insulating layer having the insulating surface;

forming a gate insulating layer over the island-shaped oxide semiconductor layer after the cleaning step;

forming a gate electrode layer over the gate insulating layer;

forming an insulating layer over the gate electrode layer to overlap with the gate electrode layer;

introducing a dopant into a part of the island-shaped oxide semiconductor layer with use of the gate electrode layer and the insulating layer as a mask;

forming a sidewall insulating layer over the gate insulating layer to cover a side surface of the gate electrode layer and a side surface of the insulating layer;

forming a conductive layer over the island-shaped oxide semiconductor layer, the gate insulating layer, the gate electrode layer, the insulating layer, and the sidewall insulating layer;

forming an interlayer insulating layer over the conductive layer; and

removing a part of the interlayer insulating layer and a part of the conductive layer with a chemical mechanical polishing method until the insulating layer over the gate electrode layer is exposed, thereby forming the source electrode layer and the drain electrode layer.

15. The method according to claim 14, further comprising the step of introducing oxygen into the oxide insulating layer.

16. The method according to claim 14, further comprising the step of introducing oxygen into the oxide semiconductor layer.

17. The method according to claim 14, further comprising the step of forming a layer containing aluminum oxide over the insulating layer, the source electrode layer, the drain electrode layer, the sidewall insulating layer, and the interlayer insulating layer.

18. The method according to claim 14, wherein the etching is a dry etching.