Oxide terminated trench MOSFET with three or four masks

• US 8,956,940 B2
• Filed: 01/27/2014
• Issued: 02/17/2015
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lui, Sik, Bhalla, Anup
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US14/165,083
• Publication Number:
  US 20140138767A1
• Time in Patent Office: 386 Days
• Field of Search: 438/270, 257/330, 257/334, 257/E27.081, 257/E21.41
• US Class Current: 438/270
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After treatment of these layers; Selection of materials for these layers
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process.

Claims

1. A method for making an insulator termination semiconductor device, comprising:

a) applying a trench mask to a semiconductor substrate;

b) etching the semiconductor substrate through the trench mask to form trenches TR1, TR2 and a plurality of trenches TR3 with three widths W1, W2 and W3, respectively, wherein the plurality of trenches TR3 are the narrowest trenches, wherein the trench TR1 surrounds the trenches TR3, wherein a portion of the width of one of the trenches TR3 overlaps the width of the trench TR1;

c) forming a gate dielectric in the trenches TR1, TR2 and TR3;

d) depositing a conductive material into the trenches TR1, TR2 and TR3, wherein a thickness of the conductive material is selected to fill up the trenches TR2 and TR3 but not the trench TR1;

e) isotropically etching back the conductive material to form gate electrodes in the trenches TR3 and the gate runner in the trench TR2, wherein the conductive material is completely removed from the portion of the trench TR1 that is not overlapped by the portion of one of the trenches TR3;

f) filling the trench TR1 with an insulator material to form an isolation trench that surrounds the gate electrodes;

g) forming a body layer in a top portion of the entire substrate;

h) forming a source layer in a top portion of the entire body layer;

wherein portions of the source layer and body layer inside a region surrounded by the isolation trench are at source potential and portions of the source layer and body layer that are outside the region surrounded by the isolation trench are at drain potential.

2. The method of claim 1 wherein k) comprises:

depositing a metal layer on top of the insulator layer;

applying a metal mask on top of the metal layer; and

etching the metal layer to form the gate metal and the source metal through the metal mask.

3. The method of claim 1 wherein f) and g) are performed without additional masks.

4. The method of claim 1 further comprising:

implanting a channel stop at a bottom of the trench TR1.

5. The method of claim 1, wherein the source and body layers inside a region surrounded by the insulator isolation trench are at source potential and the source and body regions on the outside of the insulation isolation trench are at drain potential.

6. The method of claim 1 wherein the active gates are formed in an active region and the insulator isolation trench borders said active region.

7. The method of claim 1 wherein the semiconductor substrate further comprises a heavily doped bottom layer and a less heavily doped top layer, and wherein

forming trench TR1 is performed such that trench TR1 penetrates into said heavily doped bottom layer.

8. The method of claim 1 wherein a) and b) are performed using only a single mask, and the trenches TR1, TR2, TR3 are etched simultaneously based on openings in the single mask.

9. The method of claim 1 wherein a) and b) comprise:

applying a first trench mask to a semiconductor substrate;

etching the semiconductor substrate to form trenches TR1 and TR2;

applying a second trench mask to the semiconductor substrate; and

etching the semiconductor substrate to form trenches TR3.

10. The method of claim 9 further comprising:

filling the trenches TR1 and TR2 with an insulator material; and

forming trenches TR4, wherein TR4 is formed in a top portion of the insulator material in the trench TR2.

11. The method of claim 10 wherein forming trenches TR4 is done using said second trench mask.

12. The method of claim 11 wherein c) comprises:

forming a gate dielectric in the trenches TR3; and

forming the conductive material in the trenches TR3 and TR4 to form gate electrodes in the trenches TR3 and the gate runner in the trench TR4.

13. The method of claim 1, wherein trench TR2 intersects trench TR1, and wherein the gate runner in trench TR2 continues across the intersection between the trenches TR2 and TR1.

14. An insulator termination semiconductor device comprising:

a plurality of gate trenches located in an active region, each of which includes a conductive gate electrode;

a gate runner;

an isolation trench located in a termination region that surrounds the active region,

wherein the isolation trench is filled with an insulator material to form an insulator termination for the semiconductor device; and

source and body regions throughout the device, wherein portions of the source and body regions inside the active region are at source potential and portions of the source and body regions outside the insulation isolation trench are at drain potential.

15. The device of claim 14, wherein the gate runner is formed in a gate runner trench.

16. The device of claim 15 further comprising a gate contact, wherein the gate contact and the gate runner trench are located in the active region between the gate trenches.

17. The device of claim 14 further comprising a channel stop implanted at a bottom of the insulator isolation trench.

18. The device of claim 14 wherein the semiconductor device further comprises a semiconductor substrate having a heavily doped bottom layer and a less heavily doped top layer,

wherein the insulator isolation trench penetrates into the heavily doped bottom layer.

19. The device of claim 14, wherein at least a portion of the gate runner is formed in the insulator material in the insulator isolation trench.

20. The device of claim 14, further comprising a gate contact wherein the gate contact and portions of the gate runner are located outside a region surrounded by the insulator isolation trench.

21. The device of claim 14, wherein the insulator isolation trench borders the active area.

22. The device of claim 14, wherein an extra gate runner is formed in the insulator isolation trench.