Schottky barrier diode and fabricating method thereof

• US 8,956,963 B2
• Filed: 07/02/2013
• Issued: 02/17/2015
• Est. Priority Date: 11/27/2012
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Yen, Cheng-Tyng, Lee, Lurng-Shehng, Lee, Chwan-Ying, Chu, Kuan-Wei
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): IVANOV, PAVEL G
• Application Number:
  US13/933,731
• Publication Number:
  US 20140145207A1
• Time in Patent Office: 595 Days
• Field of Search: 438570-583, 438/270, 257/341, 257/333, 257/76, 257/77, 257/486
• US Class Current: 438/571
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches.

Claims

1. A method of fabricating a Schottky barrier diode, comprising:

providing a semiconductor substrate having a first surface and a second surface positioned oppositely;

forming a plurality of trenches on the first surface of the semiconductor substrate, and each of the trenches with a first depth having a sidewall and a first bottom surface;

forming an insulating material on the first surface and on the sidewall and the first bottom surface of each of the trenches, wherein the insulating material has a first thickness on the sidewall of each of the trenches;

patterning the insulating material on the first surface and the insulating material on the sidewall of each of the trenches so as to remove the insulating material on the first surface and to define a second bottom surface in each of the trenches, wherein the second bottom surface has a second depth smaller than the first depth, and an etched portion of the insulating material on the sidewall of each of the trenches has a second thickness smaller than the first thickness; and

forming a contact metal layer at least on the first surface between the adjacent trenches.

2. The method according to claim 1, wherein the patterned insulating material has a first portion and a second portion;

wherein the first portion is extended downward from the first surface, a thickness of the first portion is equal to a difference between the first thickness and the second thickness, and a depth of the first portion is same as the second depth; and

the second portion is connected to and below the first portion, a thickness of the second portion is equal to the second thickness, and a depth of the second portion is equal to a difference between the first depth and the second depth;

wherein a ratio of the thickness of the first portion to the thickness of the second portion is between 0.01 and 0.9, and a ratio of the depth of the second portion to the first depth is between 0.01 and 0.9.

3. The method according to claim 2, wherein the step of patterning the insulating material on the first surface and on the sidewall of each of the trenches comprises:

forming a photoresist on the insulating material;

removing a portion of the photoresist to expose the insulating material on the first surface and a portion of the insulating material on the sidewalls of the trenches;

removing a portion of an upper portion of the insulating material on the sidewalls of the trenches to form the first portion; and

removing the photoresist in the trenches to form the second portion.

4. The method according to claim 1, further comprises forming the contact metal layer on the patterned insulating material.

5. The method according to claim 1, wherein before forming the contact metal layer, the method further comprises forming a conductive layer in the trenches, such that the contact metal layer is formed on the first surface between the adjacent trenches and on the conductive layer.

6. The method according to claim 5, further comprising forming a second conductive layer on the contact metal layer.

7. The method according to claim 1, wherein in the step of forming the insulating material, the insulating material is formed by a thermal oxidation process followed by a chemical vapor deposition.

8. The method according to claim 1, wherein the semiconductor substrate comprises silicon carbide (SiC) or gallium nitride (GaN).

9. The method according to claim 1, wherein the contact metal layer comprises titanium, molybdenum, aluminum, magnesium, tungsten, or silver, or an alloy or a metal silicide of the above metals.