×

Thin film transistor array substrate and manufacturing method thereof

  • US 8,957,420 B2
  • Filed: 06/24/2011
  • Issued: 02/17/2015
  • Est. Priority Date: 12/27/2010
  • Status: Active Grant
First Claim
Patent Images

1. A thin film transistor array substrate, comprising:

  • a substrate;

    a plurality of data lines, disposed on the substrate;

    a plurality of scan signal transmission lines, disposed in parallel to each other with the data lines on the substrate, with one scan signal transmission line disposed between every two adjacent data lines;

    a plurality of scan lines, disposed on the substrate and intersecting the data lines and the scan signal transmission lines, so as to define a plurality of pixel regions on the substrate;

    a plurality of thin film transistors, disposed on the substrate, each electrically connected to the corresponding scan line and the corresponding data line;

    a patterned planarization layer, configured on the substrate, wherein the patterned planarization layer has a plurality of slots, completely exposing the scan lines and the thin film transistors and extending along the scan lines;

    a plurality of common electrodes, configured on the patterned planarization layer and surrounding the corresponding pixel regions respectively;

    a protective layer, covering the data lines, the scan signal transmission lines, the scan lines, the thin film transistors, the patterned planarization layer and the common electrodes, the protective layer having a plurality of openings for exposing a portion of a drain of each of the thin film transistors;

    a plurality of pixel electrodes, configured on the protective layer and placed in the corresponding pixel regions, the pixel electrodes electrically connected to the drains through the openings.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×