Apparatus and methods for high-density chip connectivity

• US 8,957,511 B2
• Filed: 08/21/2006
• Issued: 02/17/2015
• Est. Priority Date: 08/22/2005
• Status: Active Grant

• Current Assignee: Terapede System Inc.
• Original Assignee: Terapede System Inc.
• Inventors: Vora, Madhukar B.
• Primary Examiner(s): SUN, YU-HSI DAVID
• Application Number:
  US11/508,007
• Publication Number:
  US 20070194416A1
• Time in Patent Office: 3,102 Days
• Field of Search: 257/678
• US Class Current: 257/678
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/10135 Alignment aids
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/1713 Square or rectangular array
• CPC Class Codes: H01L 2224/8014 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/20641 : larger or equal to 100 microns less than 200 microns
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a pitch of 0.6 microns, compared to a pitch of 100 microns available with today'"'"'s Ball Grid Array (BGA) technology. As a result, circuits in the mated chips can communicate via the pads with the same speed or clock frequency as if in a single chip. For example, clock rates between interconnected chips can be increased from 100 MHz to 4 GHz due to low capacitance of the interconnected pads. Because high-density arrays of pads can interconnect chips, chips can be made smaller, thereby reducing cost of chips by order(s) of magnitude.

Claims

1. An electronic device, comprising:

a first chip formed by a first process, said first chip having a plurality of first conductive pads and at least one first alignment structure; and

a second chip formed by a second process, said second chip having a plurality of second conductive pads and at least one second alignment structure, the at least one first and second alignment structures being positionally aligned and at least a subset of the first and second conductive pads being in contact with one another.

2. The electronic device according to claim 1, wherein the at least one first alignment structure defines an indentation and the at least one second alignment structure includes a protrusion having dimensions for self-alignment with the at least one first alignment structure.

3. The electronic device according to claim 2, wherein the protrusion includes a hemispherical shape.

4. The electronic device according to claim 2, wherein the protrusion has a substantially cylindrical shape.

5. The electronic device according to claim 1, wherein the at least one first alignment structure defines an indentation and the at least one second alignment structure defines an indentation, the at least one first and second alignment structures each adapted to receive a portion of a micro-ball to align the at least one first and second alignment structures.

6. The electronic device according to claim 5, wherein the at least one first alignment structure defines at least one indentation having a first dimension at a surface of the first chip and at least one indentation having a second dimension at the surface of the first chip, and

wherein the at least one second alignment structure defines at least one indentation having approximately the first dimension at a surface of the second chip and at least one indentation having approximately the second dimension at the surface of the second chip, each of the indentations having the first and second dimensions adapted to receive a portion of respectively sized micro-balls to align the at least one first and second alignment structures.

7. The electronic device according to claim 1, wherein the at least one first alignment structure defines at least one pyramid having an apex and base and extending from a surface of said first chip and the at least one second alignment structure defines at least one indentation on said second chip, wherein the at least one pyramid is configured enter the at least one protrusion and contact at an intersection of the indentation and the surface of said first chip and a location of the at least one pyramid between the apex of the at least one pyramid and the base of the at least one pyramid to cause the alignment of the first and second conductive pads.

8. The electronic device according to claim 1, wherein the at least one first alignment structure defines an indentation having a profile of a V-groove.

9. The electronic device according to claim 1, wherein said first chip includes electronic components for use in processing signals or data.

10. The electronic device according to claim 1, wherein said second chip includes memory elements.

11. The electronic device according to claim 1, wherein said first and second conductive pads have a pitch less than 100 microns.

12. The electronic device according to claim 1, wherein said first and second conductive pads have a pitch less than 10 microns.

13. The electronic device according to claim 1, wherein said first and second conductive pads have a pitch less than 1 micron.

14. The electronic device according to claim 1, wherein the aligned conductive pads are connected.

15. The electronic device according to claim 1, wherein the alignment accuracy of the aligned conductive pads is 0.5F, where F is the minimum feature size of geometric patterns formed on said first and second chips.

16. The electronic device according to claim 15, wherein the feature size is less than or equal to 100 nm.

17. The electronic device according to claim 1, wherein said at least one first alignment structure includes a protrusion and said at least one second alignment structure includes an indentation extending from a surface of said second chip into said second chip to define an opening, at least one sidewall, and a deepest location in the indentation, and wherein, in a state of alignment of said first and second at least one alignment structures, the protrusion extends into the indentation and touches at least one sidewall in a manner defining a physical void between the protrusion and the deepest location of the indentation.

18. An electronic device, comprising:

means for communicating signals between a first chip and a second chip; and

means for self-aligning the first and second chips to align and to cause said means for communicating signals between the first and second chips to be in contact with one another.

19. The electronic device according to claim 18, wherein said means for self-aligning the first and second chips includes a first means for aligning and a second means for aligning, the first means for aligning being formed on the first chip and the second means for aligning being formed on the second chip.

20. The electronic device according to claim 19, wherein the first means for aligning includes a protrusion and the second means for aligning includes an indentation extending from a surface of the second chip into the second chip to define an opening, at least one sidewall, and a deepest location in said second chip of the indentation, and wherein, in a state in which the first and second means for aligning are aligned, the protrusion extends into the indentation and touches the at least one sidewall in a manner defining a physical void between the protrusion and the deepest location of the indentation.

21. An electronic device, comprising:

a first chip having a plurality of first conductive pads having first top surfaces with first dimensions, and at least one first alignment structure; and

a second chip having a plurality of second conductive pads having second top surfaces with substantially the same dimensions as the first top surfaces of the first conductive pads and at least one second alignment structure, the at least one first and second alignment structures being positionally aligned and at least a subset of the first and second conductive pads being in contact with one another.