Output switching circuit

• US 8,957,648 B2
• Filed: 05/27/2011
• Issued: 02/17/2015
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Yoshioka, Akihito, Wakii, Takeshi
• Primary Examiner(s): PATEL, RAJNIKANT B
• Application Number:
  US13/117,717
• Publication Number:
  US 20120049811A1
• Time in Patent Office: 1,362 Days
• Field of Search: 323/222, 323/224, 323/265, 323/268, 323/272, 323282-290, 363/16, 363/17, 363/21.02, 363/25, 363/89, 363/97, 363/98, 345/211, 345/103, 345/98, 345/60, 327/158, 327/333, 327/538, 327/541, 327/540, 330/10, 330/107, 330/251, 330/207.A
• US Class Current: 323/282
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.

Claims

1. An output switching circuit, comprising:

a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output terminal at a connection node between the first and second transistors;

a comparator configured to compare an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter;

a sampling circuit configured to sample an output of the comparator based on a reference clock to generate a sampling signal having a first or a second level;

a comparison signal generating circuit configured to generate a comparison signal having the first level when the sampling signal is at the first level for a longer duration in time over a period of the comparison signal than the second level or having the second level when the sampling signal is at the first level for a shorter duration in time over the period of the comparison signal than the second level; and

a drive pulse generating unit configured to generate a first drive pulse to drive the first transistor and a second drive pulse to drive the second transistor in accordance with the comparison signal.

2. The output switching circuit according to claim 1, wherein the drive pulse generating unit is configured to pulse density modulate the comparison signal to generate the first drive pulse when the comparison signal is at the first level indicating that a voltage of the input signal is higher than a voltage of the feedback signal.

3. The output switching circuit according to claim 1, wherein the drive pulse generating unit is configured to pulse density modulate the comparison signal to generate the second drive pulse when the comparison signal is at the second level indicating that a voltage of the input signal is lower than a voltage of the feedback signal.

4. The output switching circuit according to claim 1, wherein while the comparison signal is at the first level indicating that a voltage of the input signal is higher than a voltage of the feedback signal, the drive pulse generating unit is configured to generate the first drive pulse having a pulse train with a frequency higher than a frequency of the comparison signal.

5. The output switching circuit according to claim 1, wherein while the comparison signal is at the second level indicating that a voltage of the input signal is lower than a voltage of the feedback signal, the drive pulse generating unit is configured to generate the second drive pulse having a pulse train with a frequency higher than a frequency of the comparison signal.

6. The output switching circuit according to claim 4, wherein while the comparison signal is at the first level, the drive pulse generating unit is configured to increase a time in which the first transistor is conductive.

7. The output switching circuit according to claim 6, wherein when the comparison signal is at the first level, the drive pulse generating unit is configured to control a number of conduction pulses of the first drive pulse over a second period to a first number and to replace non-conduction pulses of the first drive pulse with the conduction pulses over the second period to increase a conduction pulse width of the first drive pulse.

8. The output switching circuit according to claim 7, wherein the drive pulse generating unit is further configured to increase the conduction pulse width of the first drive pulse in a second half of the second period.

9. The output switching circuit according to claim 6, wherein the drive pulse generating unit is further configured to increase the time in which the first transistor is conductive over a second period when the comparison signal is maintained at the first level over multiple second periods.

10. The output switching circuit according to claim 5, wherein while the comparison signal is at the second level, the drive pulse generating unit is configured to increase a time in which the second transistor is conducive.

11. The output switching circuit according to claim 10, wherein when the comparison signal is at the second level, the drive pulse generating unit is configured to control a number of conduction pulses of the second drive pulse over a second period to a second number and to replace non-conduction pulses of the second drive pulse with the conduction pulses over the second period to increase a conduction pulse width of the second transistor.

12. The output switching circuit according to claim 11, wherein the drive pulse generating unit is further configured to increase the conduction pulse width of the second drive pulse in a second half of the second period.

13. The output switching circuit according to claim 10, wherein when the comparison signal is at the second level, the drive pulse generating unit is configured to increase a number of conduction pulses of the second drive pulse.

14. The output switching circuit according to claim 13, wherein the drive pulse generating unit is configured to increase the number of conduction pulses of the second drive pulse in a second half of the second period.

15. The output switching circuit according to claim 10, the drive pulse generating unit is further configured to increase the time in which the second transistor is conductive over a second period when the comparison signal is maintained at the first level over multiple second periods.

16. An output switching circuit, comprising:

a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output terminal at a connection node between the first and second transistors;

a comparison unit configured;

to sample an analog signal according to a sampling signal, the sampling signal having a first level and a second level, and

to generate a comparison signal having the first level when the sampling signal is at the first level for a longer duration in time over a period of the comparison signal than the second level or having the second level when the sampling signal is at the first level for a shorter duration in time over the period of the comparison signal than the second level; and

a drive pulse generating unit configured to generate a first drive pulse to drive the first transistor and a second drive pulse to drive the second transistor in accordance with the comparison signal.

17. The output switching circuit according to claim 16, wherein the drive pulse generating unit is configured to pulse density modulate the comparison signal to generate the first drive pulse when the comparison signal is at the first level indicating that a voltage of the input signal is higher than a voltage of the feedback signal.

18. The output switching circuit according to claim 16, wherein the drive pulse generating unit is configured to pulse density modulate the comparison signal to generate the second drive pulse when the comparison signal is at the second level indicating that a voltage of the input signal is lower than a voltage of the feedback signal.

19. The output switching circuit according to claim 16, wherein while the comparison signal is at the first level indicating that a voltage of the input signal is higher than a voltage of the feedback signal, the drive pulse generating unit is configured to generate the first drive pulse having a pulse train with a frequency higher than a frequency of the comparison signal.