Startup of DC-DC converters utilizing multiple power segments

• US 8,957,657 B2
• Filed: 09/17/2012
• Issued: 02/17/2015
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zhao, Bin, Lee, Victor
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Quddus, Nusrat
• Application Number:
  US13/621,380
• Publication Number:
  US 20130249519A1
• Time in Patent Office: 883 Days
• Field of Search: 323/238, 323/266, 323282-290
• US Class Current: 323/284
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H03K 17/166 Soft switching

Abstract

Generally, this disclosure provides methods and systems for improved startup for DC-DC converters that reduce input voltage droop, in-rush current and output voltage jumps. The system may include a power stage circuitry including a plurality of power segments coupled in parallel, the power stage circuitry is coupled between an input voltage and output stage circuitry and configured to deliver power to a load coupled to the output stage circuitry. The system may further include PWM and power stage controller circuitry configured to sequentially and progressively activate the plurality of power segments to limit an input in-rush current from the input voltage during a ramp up period and output voltage at the output stage circuitry.

Claims

1. A DC-DC converter system, comprising:

power stage circuitry comprising a plurality of power segments coupled in parallel, said power stage circuitry is coupled between an input voltage and output stage circuitry and configured to deliver power to a load coupled to said output stage circuitry; and

pulse width modulation (PWM) and power stage controller circuitry configured to sequentially and progressively activate said plurality of power segments to limit an input in-rush current from said input voltage during a ramp up period and output voltage at said output stage circuitry, said PWM and power stage controller circuitry comprising a voltage threshold selection and comparator circuit configured to select an output voltage threshold from a plurality of output voltage thresholds and compare said selected output voltage threshold to said output voltage and to activate one of said power segments associated with said selected output voltage threshold.

2. The system of claim 1, wherein said PWM and power stage controller circuitry further comprises a timer circuit configured to activate one of said power segments in response to a current limit condition existing for one of a plurality of current limit timer values, said current limit timer value associated with said power segment.

3. The system of claim 2, wherein said plurality of output voltage threshold values and said plurality of current limit timer values are pre-determined based on the topology of said DC-DC converter.

4. The system of claim 2, wherein said plurality of output voltage threshold values and said plurality of current limit timer values are programmable.

5. The system of claim 1, wherein said plurality of output voltage threshold are selected in increasing voltage values as said plurality of power segments are sequentially and progressively activated.

6. The system of claim 1, wherein at least two of said progressively activated power segments is on a high-side of said DC-DC converter.

7. The system of claim 1, wherein at least two of said progressively activated power segments is on a low-side of said DC-DC converter.

8. The system of claim 1, wherein said DC-DC converter system is configured as a buck converter topology.

9. The system of claim 1, wherein said DC-DC converter system is configured as a boost converter topology.

10. The system of claim 1, wherein said power segments comprise FET switch circuitry.

11. The system of claim 1, wherein at least one of said power segments comprises diode switch circuitry.

12. A method, comprising:

determining a plurality of output voltage threshold values and a plurality of current limit timer values;

activating a first power segment of a DC-DC converter;

monitoring output voltage and current;

determining if said output voltage equals a first of said output voltage threshold values;

determining if a first of said current limit timer values has timed out; and

activating a second power segment of said DC-DC converter if said output voltage equals said first output voltage threshold value or if said first current limit timer value has timed out.

13. The method of claim 12, further comprising:

determining if said output voltage equals a second of said output voltage threshold values in response to said activating of said second power segment;

determining if a second of said current limit timer values has timed out; and

activating a third power segment of said DC-DC converter if said output voltage equals said second output voltage threshold value or if said second current limit timer value has timed out.

14. The method of claim 12, wherein said first and said second power segments are on a high-side of said DC-DC converter.

15. The method of claim 12, wherein said first and said second power segments are on a low-side of said DC-DC converter and said DC-DC converter is a boost converter.

16. The method of claim 12, wherein said plurality of output voltage threshold values and said plurality of current limit timer values are pre-determined based on the topology of said DC-DC converter.

17. The method of claim 12, wherein said plurality of output voltage threshold values and said plurality of current limit timer values are programmable.

18. The method of claim 13, wherein said second output voltage threshold is greater than said first output voltage threshold.