Wafer level package resistance monitor scheme

• US 8,957,694 B2
• Filed: 05/22/2012
• Issued: 02/17/2015
• Est. Priority Date: 05/22/2012
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hu, Kunzhong, Zhong, Chonghua, Law, Edward
• Primary Examiner(s): Baldridge, Benjamin M
• Application Number:
  US13/477,313
• Publication Number:
  US 20130314120A1
• Time in Patent Office: 1,001 Days
• Field of Search: 324/762.03
• US Class Current: 324/762.03
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold.

Claims

1. An integrated circuit, comprising:

a monitoring circuit; and

a monitored circuit connected with the monitoring circuit, the monitored circuit comprising an in-fab redistribution layer connector and a post-fab redistribution layer connector; and

the monitoring circuit configured to determine at a stage before fabrication of an additional layer of the integrated circuit, if a resistance of a connection between the in-fab redistribution layer connector and the post-fab redistribution layer connector exceeds a threshold, the resistance being indicative of a thickness of an oxide layer formed between the in-fab redistribution layer connector and the post-fab redistribution layer connector.

2. The integrated circuit of claim 1 where the monitoring circuit comprises a wheatstone bridge circuit to determine the resistance when a voltage is applied.

3. The integrated circuit of claim 1 where the monitoring circuit includes a fuse trace to break when resistance of the connection exceeds the threshold.

4. The integrated circuit of claim 3 where the fuse is positioned in an aluminum pad layer.

5. The integrated circuit of claim 1 where the monitoring circuit includes an in-fab trace positioned in an aluminum pad layer.

6. The integrated circuit of claim 5 where the monitoring circuit includes a post-fab trace connected with the in-fab trace.

7. The integrated circuit of claim 1 where the monitored circuit comprises a wafer level ball grid array package structure.

8. The integrated circuit of claim 1 where, the in-fab redistribution layer connector is included in a first layer of a package structure of the integrated circuit, and the post-fab redistribution layer connector is included in a second layer of the package structure, the second layer formed on the first layer ahead of the stage and before the additional layer is formed in the package structure.

9. An integrated circuit, comprising:

an in-fab redistribution layer connector;

a post-fab redistribution layer connector connected with the in-fab redistribution layer connector to make an electrical connection;

an oxide layer located between the in-fab redistribution layer connector and the post-fab redistribution layer connector, the oxide layer providing a connector resistance to the electrical connection; and

a monitoring circuit connected with the oxide layer, the monitoring circuit to determine if a resistance between the in-fab redistribution layer connector and the post-fab redistribution layer connector caused by the oxide layer exceed a threshold.

10. The integrated circuit of claim 9 where the monitoring circuit includes an in-fab trace positioned in an aluminum pad layer.

11. The integrated circuit of claim 10 where the monitoring circuit includes a post-fab trace connected with the in-fab trace.

12. The integrated circuit of claim 9 where the monitoring circuit includes a fuse trace to break when the connector resistance exceeds the threshold.

13. The integrated circuit of claim 12 where the fuse is positioned in an aluminum pad layer.

14. The integrated circuit of claim 9 where the oxide layer comprises an aluminum oxide layer.

15. The integrated circuit of claim 9 where the monitoring circuit comprises a wheatstone bridge circuit.

16. A monitoring circuit for an integrated circuit, comprising:

an in-fab trace;

a post-fab trace connected with the in-fab trace;

an oxide layer positioned between the in-fab trace and the post-fab trace; and

a fuse trace connected with the in-fab trace, where the fuse trace is operable to break if a resistance caused by the oxide layer exceeds a threshold, and where the in-fab trace, the post-fab trace and the fuse trace comprise a wheatstone bridge circuit.

17. The monitoring circuit of claim 16 where the in-fab trace is located in an aluminum pad layer of the integrated circuit.

18. The monitoring circuit of claim 16 where the post-fab trace comprises a redistribution layer connector.