Phase frequency detector

• US 8,957,705 B2
• Filed: 09/14/2012
• Issued: 02/17/2015
• Est. Priority Date: 09/14/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jia, Wenyan, Li, Shenggao, Spagna, Fulvio
• Primary Examiner(s): O NEILL, PATRICK
• Application Number:
  US13/617,233
• Publication Number:
  US 20140077841A1
• Time in Patent Office: 886 Days
• Field of Search: 327/2, 327/3, 327/5, 327 7- 10, 327/12, 327/147, 327/150, 327/156, 327/159, 331/17, 331/25, 375/373, 375/376
• US Class Current: 327/3
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03D 13/00 Circuits for comparing the phase or frequency of two mutually-independent oscillations measuring phase G01R25/00; phase-discriminators with yes/no output G01R25/005
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence

Abstract

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

Claims

1. An apparatus comprising:

a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first digital output indicating the coarse phase difference; and

a second PFD to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second digital output indicating the fine phase difference;

an adder, said adder having a first input coupled to an output of said first PFD, said adder having a second input coupled to an output of said second PFD, said adder to generate a sum phase difference representative of a phase difference between said first and second clock signals.

2. The apparatus claim 1, wherein the first PFD is to provide a substantially linear characteristic over a wide phase difference of the first clock signal and the second clock signal.

3. The apparatus of claim 1, wherein the first and second PFDs are to operate in parallel.

4. The apparatus of claim 1, wherein the first and second PFDs are to operate sequentially.

5. The apparatus of claim 1, wherein the first PFD is a time-to-digital converter (TDC).

6. The apparatus of claim 1, wherein the second PFD is a bang-bang PFD (BBPFD).

7. The apparatus of claim 6, wherein the BBPFD comprises a first stage to detect edges of the first and second clock signals, the first stage to generate a phase difference between the first and second clock signals.

8. The apparatus of claim 1 wherein an output of the adder is to provide a code having most significant bits determined by the first PFD and least significant bits determined by the second PFD.

9. The apparatus of claim 8, wherein an output signal of the first PFD is padded with 0s in least significant bit locations.

10. The apparatus of claim 1, wherein an output signal of the second PFD indicates a fixed quantity to be added/subtracted by the adder to/from the output of the first PFD.

11. The apparatus of claim 1, wherein the first and second PFDs and the adder are part of a PFD of a phase locked loop (PLL) or a delay locked loop (DLL).

12. The apparatus of claim 11, wherein the first and second PFDs and the adder are part of a PFD of a PLL and the PLL is a digital PLL.

13. The apparatus of claim 1, wherein the first signal is a reference clock signal and the second signal is a feedback clock signal.

14. A phase frequency detector (PFD) comprising:

a time-to-digital converter (TDC) to determine a coarse phase difference between a reference clock signal and a feedback clock signal, the TDC to generate a first output indicating the coarse phase difference; and

a bang-bang PFD (BBPFD), coupled to the TDC, to determine a fine phase difference between the reference clock signal and the feedback clock signal, the BBPFD to generate a second output indicating the fine phase difference;

an adder to sum the first and second outputs.

15. The PFD of claim 14 , wherein the TDC is to provide a substantially linear transfer function over a period of the reference clock signal.

16. The PFD of claim 15, wherein the transfer function is expressed as a digital code as a function of phase difference.

17. A system comprising:

a memory;

a processor, coupled to the memory, the processor including;

a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first digital output indicating the coarse phase difference; and

a second PFD to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second digital output indicating the fine phase difference; and

an adder to sum the first and second digital outputs;

a wireless interface for communicatively coupling the processor to another device.

18. The system of claim 17, wherein the processor further comprises an adder to sum the first and second digital outputs to generate a resultant phase difference between the first clock signal and the second clock signal.

19. The system of claim 17 further comprises a display unit.

20. The system of claim 17, wherein the first PFD is a time-to-digital converter (TDC).

21. The system of claim 17, wherein the second PFD is a bang-bang PFD (BBPFD).