Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof
First Claim
1. A method of forming a memory having memory elements arranged in a 3D memory layer defined by rectangular coordinates having x, y and z-directions and with a plurality of planes stacked in the z-direction, comprising:
- providing a semi-conductor substrate;
forming metal lines on the semi-conductor substrate;
forming in a pillar select layer a 2-D array in the x-y plane of pillar select devices on top of the metal lines, whereinsaid forming the 3D memory layer further includes;
forming a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;
forming a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of bit line pillars in the individual planes;
the hit line pillars and word lines cross adjacent each other at a plurality of locations across the individual planes;
forming a plurality of non-volatile re-programmable memory elements individually connected through circuits between the bit line pillars and the word lines adjacent the crossings thereof;
such that the pillar select devices are switching between the 3D memory layer and the metal lines; and
forming conductive riser columns connected to individual word lines in a plane from a top surface of the plurality of planes stacked in the z-direction.
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Accused Products
Abstract
A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate.
68 Citations
12 Claims
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1. A method of forming a memory having memory elements arranged in a 3D memory layer defined by rectangular coordinates having x, y and z-directions and with a plurality of planes stacked in the z-direction, comprising:
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providing a semi-conductor substrate; forming metal lines on the semi-conductor substrate; forming in a pillar select layer a 2-D array in the x-y plane of pillar select devices on top of the metal lines, wherein said forming the 3D memory layer further includes; forming a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; forming a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of bit line pillars in the individual planes;
the hit line pillars and word lines cross adjacent each other at a plurality of locations across the individual planes;forming a plurality of non-volatile re-programmable memory elements individually connected through circuits between the bit line pillars and the word lines adjacent the crossings thereof; such that the pillar select devices are switching between the 3D memory layer and the metal lines; and forming conductive riser columns connected to individual word lines in a plane from a top surface of the plurality of planes stacked in the z-direction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification