Clock and data recovery with infinite pull-in range

• US 8,958,513 B1
• Filed: 03/15/2013
• Issued: 02/17/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Novellini, Paolo, Kellermann, Martin J.
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US13/837,864
• Time in Patent Office: 704 Days
• Field of Search: 375322-327, 375/294, 375/215, 375354-355, 375/373, 375/375, 375/376
• US Class Current: 375/355
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop
• CPC Class Codes: H04L 7/046 using a dotting sequence
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A device and method for clock and data recovery are disclosed. For example, an integrated circuit comprises a first branch for recovering a clock signal from an input signal. The first branch includes a phase and frequency detector for detecting a phase and a frequency of the clock signal and a numerically controlled oscillator that is controlled by the phase and the frequency of the clock signal from the phase and frequency detector. The integrated circuit also includes a second branch for recovering a data signal from the input signal. The second branch includes a pre-settable numerically controlled oscillator that is pre-settable with the phase and the frequency of the clock signal from the numerically controlled oscillator. The second branch also includes a sample selector that is controlled by the pre-settable numerically controlled oscillator for recovering the data signal.

Claims

1. An integrated circuit, comprising:

a first branch for recovering a clock signal from an input signal, the first branch comprising;

a phase and frequency detector for detecting a phase and a frequency of the clock signal;

a numerically controlled oscillator that is controlled by the phase and the frequency of the clock signal from the phase and frequency detector; and

a pattern detector for detecting a clock pattern of the clock signal; and

a second branch for recovering a data signal from the input signal, the second branch comprising;

a pre-settable numerically controlled oscillator, wherein the pre-settable numerically controlled oscillator is pre-settable with the phase and the frequency of the clock signal from the numerically controlled oscillator, wherein the pre-settable numerically controlled oscillator is further controlled by the pattern detector, wherein when the clock pattern is detected by the pattern detector, the pattern detector via a trigger signal causes the pre-settable numerically controlled oscillator to be pre-set with the phase and the frequency of the clock signal from the numerically controlled oscillator; and

a sample selector that is controlled by the pre-settable numerically controlled oscillator for recovering the data signal.

2. The integrated circuit of claim 1, wherein the input signal comprises an alternating pattern of the clock signal and the data signal.

3. The integrated circuit of claim 1, wherein the second branch further comprises:

a delay element, for delaying the input signal by at least one clock cycle.

4. The integrated circuit of claim 1, wherein the clock pattern comprises an alternating bit pattern of ones and zeros.

5. The integrated circuit of claim 1, wherein the pre-settable numerically controlled oscillator blocks the phase and the frequency of the clock signal from the numerically controlled oscillator when the trigger signal is not received.

6. The integrated circuit of claim 1, wherein the second branch further comprises:

a phase detector in a feedback loop with the pre-settable numerically controlled oscillator, wherein the phase detector is for receiving the input signal and detecting a phase of the data signal in the input signal.

7. The integrated circuit of claim 1, wherein the first branch further comprises a sample selector that is controlled by the numerically controlled oscillator for selecting samples from the input signal.

8. The integrated circuit of claim 1, further comprising:

a splitter for splitting the input signal to the first branch and to the second branch.

9. The integrated circuit of claim 1, wherein the numerically controlled oscillator and the phase and frequency detector in the first branch comprise a feedback loop.

10. The integrated circuit of claim 1, wherein the input signal comprises digitally oversampled data.

11. The integrated circuit of claim 1, wherein the numerically controlled oscillator comprises an N-bit register.

12. The integrated circuit of claim 1, wherein the pre-settable numerically controlled oscillator comprises a multiplexer and an N-bit register, wherein the multiplexer is for selecting a phase from the numerically controlled oscillator in the first branch or a phase from a phase detector in the second branch.

13. The integrated circuit of claim 1, wherein the first branch further comprises:

a low-pass filter between the phase and frequency detector and the numerically controlled oscillator.

14. The integrated circuit of claim 13, wherein the low-pass filter comprises a proportional and integral filter.

15. The integrated circuit of claim 13, wherein the second branch further comprises:

a pre-settable low-pass filter that is controlled by the low-pass filter in the first branch and a pattern detector in the first branch.

16. The integrated circuit of claim 15, wherein the pre-settable low-pass filter comprises, a proportional and integral filter, wherein the proportional and integral filter comprises a multiplexer for selecting a status from the low-pass filter of the first branch or a phase detector error from a phase detector in the second branch.

17. A method, comprising:

recovering a clock signal from an input signal, the recovering the clock signal comprising;

detecting a phase and a frequency of the clock signal; and

driving a numerically controlled oscillator by the phase and the frequency of the clock signal that is detected;

detecting a clock pattern of the clock signal; and

recovering a data signal from the input signal, wherein the recovering the data signal comprises;

pre-setting a pre-settable numerically controlled oscillator with a phase and a frequency from the numerically controlled oscillator via a trigger signal when the clock pattern is detected; and

selecting data samples from the input signal based upon a phase and frequency from the pre-settable numerically controlled oscillator.

18. An integrated circuit, comprising:

a phase and frequency detector for detecting a phase and a frequency of a clock signal in an input signal;

a numerically controlled oscillator that is controlled by the phase and the frequency of the clock signal from the phase and frequency detector;

a pattern detector for detecting a clock pattern of the clock signal;

a pre-settable numerically controlled oscillator, wherein the pre-settable numerically controlled oscillator is pre-settable with the phase and the frequency of the clock signal from the numerically controlled oscillator, wherein the pre-settable numerically controlled oscillator is further controlled by the pattern detector, wherein when the clock pattern is detected by the pattern detector, the pattern detector via a trigger signal causes the pre-settable numerically controlled oscillator to be pre-set with the phase and the frequency of the clock signal from the numerically controlled oscillator; and

a sample selector that is controlled by the pre-settable numerically controlled oscillator for recovering a data signal in the input signal.