Flash storage controller execute loop

• US 8,959,282 B2
• Filed: 05/10/2013
• Issued: 02/17/2015
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Douglas A.
• Primary Examiner(s): Li, Aimee
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US13/892,214
• Publication Number:
  US 20130339582A1
• Time in Patent Office: 648 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Claims

1. A method, comprising:

at a storage controller in a system in which the storage controller is operatively coupled to a flash memory module comprising a plurality of flash memory groups, each flash memory group corresponding to a distinct flash port of the storage controller, each flash port comprising a processor;

writing state information into a first data structure related to performing a first flash read or write in a first flash memory group of the plurality of flash memory groups, the state information reflecting command and address information to be sent to the first flash memory group;

placing a first pointer to the first data structure on a first queue;

writing state information into a second data structure related to performing a second flash read or write in a second flash memory group of the plurality of flash memory groups, the state information reflecting command and address information to be sent to the second flash memory group;

placing a second pointer to the second data structure on a second queue;

writing state information into a third data structure related to performing a third flash read or write in a third flash memory group of the plurality of flash memory groups, the state information reflecting command and address information to be sent to the third flash memory group;

placing a third pointer to the third data structure on a third queue;

reading the first pointer from the first queue;

based on the first pointer, reading the first data structure state information;

based on the first data structure state information, transmitting address and command information to the first flash memory group;

modifying the first data structure state information to reflect the need for a first buffer;

reading the second pointer from the second queue;

based on the second pointer, reading the second data structure state information;

based on the second data structure state information, transmitting address and command information to the second flash memory group;

modifying the second data structure state information to reflect the need for a second buffer;

reading the third pointer from the third queue;

based on the third pointer, reading the third data structure state information;

based on the third data structure state information, transmitting address and command information to the third flash memory group;

modifying the third data structure state information to reflect the need for a third buffer;

reading the first pointer from the first queue;

determining whether the first buffer is available;

when the first buffer is available, initiating a first transfer between the first flash memory group and the first buffer, and modifying the first data structure state information to reflect the first transfer; and

reading the second pointer from the second queue.

2. The method of claim 1, in which:

the first data structure, the second data structure and the third data structure are related to the same host command.

3. The method of claim 1, in which:

the first data structure relates to a first host command and the second data structure relates to a second host command.

4. The method of claim 3, in which:

the first host command is a read command and the second host command is a write command.

5. The method of claim 1, further comprising:

reading the first pointer from the first queue is preceded by a step of evaluating a fourth queue and determining that the fourth queue does not contain any pointer to any data structure.

6. The method of claim 1, further comprising:

determining whether the second buffer is available;

when the second buffer is available, initiating a second transfer between the second flash memory group and the second buffer, and modifying the second data structure state information to reflect the second transfer;

reading the third pointer from the third queue;

determining whether the third buffer is available;

when the third buffer is available, initiating a third transfer between the third flash memory group and the third buffer, and modifying the third data structure state information to reflect the third transfer; and

reading the first pointer from the first queue.

7. The method of claim 1, further comprising:

following the completion of flash read or write operations relating to the first data structure, removing the first pointer from the first queue.

8. The method of claim 7, further comprising:

subsequent to removal of the first pointer from the first queue, reading a fourth pointer from the first queue, the fourth pointer relating to a fourth data structure.

9. The method of claim 1, in which:

initiating the first transfer between the first flash memory group and the first buffer comprises initiating a DMA transfer.

10. The method of claim 1, in which:

transmitting address and command information to the first flash memory group triggers a read from flash memory devices of the first flash memory group to the first buffer, and said read is performed concurrently with said transmitting address and command information to the second flash memory group.

11. A storage controller configured to be coupled to a flash memory module comprising a plurality of flash memory groups, comprising:

a host interface configured to receive one or more host commands;

a plurality of flash ports, including a distinct flash port corresponding to each flash memory group of the plurality of flash memory groups;

a plurality of processors;

memory storing one or more programs, which when executed by respective processors of the plurality of processors, cause the storage controller to perform a method comprising;

writing state information into a first data structure related to performing a first flash read or write in a first flash memory group of the plurality of flash memory groups, the state information reflecting command and address information to be sent to the first flash memory group;

placing a first pointer to the first data structure on a first queue;

writing state information into a second data structure related to performing a second flash read or write in a second flash memory group of the plurality of flash memory groups, the state information reflecting command and address information to be sent to the second flash memory group;

placing a second pointer to the second data structure on a second queue;

writing state information into a third data structure related to performing a third flash read or write in a third flash memory group of the plurality of flash memory groups, the state information reflecting command and address information to be sent to the third flash memory group;

placing a third pointer to the third data structure on a third queue;

reading the first pointer from the first queue;

based on the first pointer, reading the first data structure state information;

based on the first data structure state information, transmitting address and command information to the first flash memory group;

modifying the first data structure state information to reflect the need for a first buffer;

reading the second pointer from the second queue;

based on the second pointer, reading the second data structure state information;

based on the second data structure state information, transmitting address and command information to the second flash memory group;

modifying the second data structure state information to reflect the need for a second buffer;

reading the third pointer from the third queue;

based on the third pointer, reading the third data structure state information;

based on the third data structure state information, transmitting address and command information to the third flash memory group;

modifying the third data structure state information to reflect the need for a third buffer;

reading the first pointer from the first queue;

determining whether the first buffer is available;

when the first buffer is available, initiating a first transfer between the first flash memory group and the first buffer, and modifying the first data structure state information to reflect the first transfer; and

reading the second pointer from the second queue.

12. The storage controller of claim 11, in which:

the first data structure, the second data structure and the third data structure are related to the same host command.

13. The storage controller of claim 11, in which:

the first data structure relates to a first host command and the second data structure relates to a second host command.

14. The storage controller of claim 13, in which:

the first host command is a read command and the second host command is a write command.

15. The storage controller of claim 11, wherein the one or more programs further include instructions that, when executed by respective processors of the plurality of processors, cause the storage controller to:

evaluate a fourth queue and determine that the fourth queue does not contain any pointer to any data structure before reading the first pointer from the first queue.

16. The storage controller of claim 11, wherein the one or more programs further include instructions that, when executed by respective processors of the plurality of processors, cause the storage controller to:

determine whether the second buffer is available;

when the second buffer is available, initiate a second transfer between the second flash memory group and the second buffer, and modify the second data structure state information to reflect the second transfer;

read the third pointer from the third queue;

determine whether the third buffer is available;

when the third buffer is available, initiate a third transfer between the third flash memory group and the third buffer, and modify the third data structure state information to reflect the third transfer; and

read the first pointer from the first queue.

17. The storage controller of claim 11, wherein the one or more programs further include instructions that, when executed by respective processors of the plurality of processors, cause the storage controller to:

following the completion of flash read or write operations relating to the first data structure, remove the first pointer from the first queue.

18. The storage controller of claim 17, wherein the one or more programs further include instructions that, when executed by respective processors of the plurality of processors, cause the storage controller to:

subsequent to removal of the first pointer from the first queue, read a fourth pointer from the first queue, the fourth pointer relating to a fourth data structure.

19. The storage controller of claim 11, in which:

initiating the first transfer between the first flash memory group and the first buffer comprises initiating a DMA transfer.

20. The storage controller of claim 11, in which:

transmitting address and command information to the first flash memory group triggers a read from flash memory devices of the first flash memory group to the first buffer, and said read is performed concurrently with said transmitting address and command information to the second flash memory group.