Flash storage controller execute loop

• US 8,959,283 B2
• Filed: 12/20/2013
• Issued: 02/17/2015
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Douglas A.
• Primary Examiner(s): Li, Aimee
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US14/136,549
• Publication Number:
  US 20140108715A1
• Time in Patent Office: 424 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Claims

1. A method including performing the following steps by a first processor of a first flash port of a plurality of flash ports of a storage controller, the storage controller configured to be coupled to a flash memory module, each flash port of the plurality of flash ports corresponding to a flash memory group of the flash memory module, each flash port comprising an associated processor:

checking a first state variable in a first data structure selected from a first queue for a first bank of a first flash memory group corresponding to the first flash port;

in accordance with a determination that the first state variable indicates a predefined stage of command processing, initiating a first task, wherein the first task is related to reading data from or writing data to the first bank of the first flash memory group, and updating the first state variable in the first data structure;

in accordance with a determination that the first state variable indicates a first resource is required, checking if the first resource is available;

in accordance with a determination that the first resource is available, processing and completing the first task, and setting a return value in the first flash port as busy;

checking a second state variable in a second data structure selected from a second queue for a second bank of the first flash memory group corresponding to the first flash port;

in accordance with a determination that the second state variable indicates the predefined stage of command processing, initiating a second task, wherein the second task is related to reading data from or writing data to the second bank of the first flash memory group, and updating the second state variable in the second data structure;

in accordance with a determination that the second state variable indicates a second resource is required, checking if the second resource is available;

in accordance with a determination that the second resource is available, processing and completing the second task, and setting a return value in the first flash port as busy; and

repeating the above steps until the first state variable indicates that the first task is complete, removing the first data structure from the first queue and continue performing the above steps until the second state variable indicates that the second task is complete, and removing the second data structure from the second queue;

wherein

the first data structure represents a first host command from a first host and the second data structure represents a second host command from a second host.

2. The method of claim 1, wherein the first data structure is a first page request and the second data structure is a second page request.

3. The method of claim 1, wherein the first host command and the second host command each comprise one of a read command and a write command.

4. The method of claim 1, wherein updating the first state variable and updating the second state variable each comprise setting the state of the respective state variable to indicate the respective resource is required.

5. The method of claim 1, wherein the first resource or the second resource comprises a stage buffer.

6. The method of claim 1, further comprising the step of setting the first flash port into a sleep mode.

7. A storage controller configured to be coupled to a flash memory module having a plurality of flash memory groups, comprising:

a host interface configured to receive a plurality of host commands;

a plurality of flash ports, each flash port corresponding to a flash memory group of the flash memory module, each flash port comprising an associated processor;

a plurality of processors;

memory storing one or more programs, which when executed by respective processors of the plurality of processors cause the storage controller to perform a method comprising;

for each flash port of the plurality of flash ports;

checking a first state variable in a first data structure selected from a first queue for a first bank of the flash memory group corresponding to the flash port;

in accordance with a determination that the first state variable indicates a predefined stage of command processing, initiating a first task, wherein the first task is related to reading data from or writing data to the first bank of the flash memory group, and updating the first state variable in the first data structure;

in accordance with a determination that the first state variable indicates a first resource is required, checking if the first resource is available;

in accordance with a determination that the first resource is available, processing and completing the first task, and setting a return value in the flash port as busy;

checking a second state variable in a second data structure selected from a second queue for a second bank of the flash memory group corresponding to the flash port;

in accordance with a determination that the second state variable indicates the predefined stage of command processing, initiating a second task, wherein the second task is related to reading data from or writing data to the second bank of the flash memory group, and updating the second state variable in the second data structure;

in accordance with a determination that the second state variable indicates a second resource is required, checking if the second resource is available;

in accordance with a determination that the second resource is available, processing and completing the second task, and setting a return value in the flash port as busy; and

repeating the above steps until the first state variable indicates that the first task is complete, removing the first data structure from the first queue and continue performing the above steps until the second state variable indicates that the second task is complete, and removing the second data structure from the second queue;

wherein

the first data structure represents a first host command from a first host and the second data structure represents a second host command from a second host.

8. The storage controller of claim 7, wherein the first data structure is a first page request and the second data structure is a second page request.

9. The storage controller of claim 7, wherein the first host command and the second host command each comprise one of a read command and a write command.

10. The storage controller of claim 7, wherein updating the first state variable and updating the second state variable each comprise setting the state of the respective state variable to indicate the respective resource is required.

11. The storage controller of claim 7, wherein the first resource or the second resource comprises a stage buffer.

12. The storage controller of claim 7, wherein the one or more programs further include instructions that, when executed by the one or more processors, cause the storage controller to set the flash port into a sleep mode.