Identifying invalid cache data

• US 8,959,288 B1
• Filed: 08/03/2010
• Issued: 02/17/2015
• Est. Priority Date: 07/29/2010
• Status: Expired due to Fees

• Current Assignee: Violin Systems LLC
• Original Assignee: Violin Memory Incorporated
• Inventors: de la Iglesia, Erik, Sikdar, Som, Dommeti, Sivaram, Knox, Garry
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US12/849,652
• Time in Patent Office: 1,659 Days
• Field of Search: 711/133, 711/167, 711/169, 711/E12.002, 711/152
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

Cache lines are identified that provide incorrect data for read requests. The cache lines are invalidated before the incorrect data causes processing failure conditions. The cache lines providing incorrect data may be detected according to a number of the same read requests to the same cache lines. The cache lines may also be identified according to an amount of time between the same read requests to the same cache lines. The same read requests to the same cache lines may be identified according to associated start addresses and address lengths.

Claims

1. An apparatus, comprising:

a memory configured to store data as cache lines; and

logic circuitry configured to;

characterize memory access requests of a plurality of memory access requests by;

a read start address; and

a read length,

wherein the logic circuitry is configured to increment a count value when a next memory access request to the cache line is characterized by a same read start address as the read start address and a same read length as the read length;

identify potentially incorrect stored data in a cache line of the cache lines based on the characterized memory access requests of at least two memory access requests of the plurality of memory requests; and

invalidate the potentially incorrect stored data in the cache line.

2. The apparatus of claim 1 wherein the logic circuitry is configured to reset the count value when the next memory access request has a different read start address than the read start address or the next memory access request has a different read length than the read length.

3. The apparatus according to claim 2 wherein the logic circuitry is configured to identify the potentially incorrect stored data in the cache line when the count value is above a given count threshold.

4. The apparatus of claim 3 wherein the logic circuitry is configured to:

set a time value a corresponding to the memory access request to the stored data in the cache line having the start address and the read length; and

reset the time value when the next memory access request has the same read start address as the read start address and a same read length as the read length.

5. The apparatus according to claim 4 wherein the logic circuitry is configured to invalidate the cache line with identified potentially incorrect stored data when the count value is above the given count threshold and a time value corresponding to the next memory access request is within a given time threshold of time value.

6. The apparatus according to claim 1 wherein the memory and logic circuitry comprise a storage proxy configured to intercept the memory access request sent from initiators to storage targets and provide data responsive to the memory access request either from storage targets or from the memory.

7. The apparatus of claim 6 wherein the logic circuitry in the storage proxy is configured to invalidate the requested cache lines and forward the memory access request to the storage targets when characteristics of the memory access request indicates that the requested stored data in the cache line is potentially incorrect.

8. The apparatus according to claim 1 identification is determined by a number of times memory access requests with a same characteristic are made to the cache line.

9. The apparatus according to claim 1 wherein the identification is determined by an amount of time between memory access requests with a same characteristic are made to the cache line.

10. The apparatus of claim 1, wherein the apparatus is storage proxy disposed between a initiator and a target.

11. The apparatus of claim 1, wherein the logic circuitry includes a processor.

12. A non-volatile computer readable storage medium containing instructions executable by a computer, the instructions when executed by the computer comprising:

storing a first read start address for a previous read operation accessing a cache line;

storing a first read length for the previous read operation;

identifying a second read start address for a subsequent read operation accessing the cache line;

identifying a second read length for the subsequent read operation;

identifying the subsequent read operation as a reread operation when the first read start address matches the second read start address and the first read length matches the second read length;

incrementing a count value when the subsequent read operation is identified as the reread operation; and

invalidating the cache line when the count value is above a given threshold.

13. The computer readable medium according to claim 12 further comprising resetting the count value when the subsequent read operation is not the reread operation.

14. The computer readable medium according to claim 12 further comprising setting the threshold below a reread failure condition of a processing element sending the read operations.

15. The computer readable medium according to claim 12 further comprising replacing the stored first read start address with the second read start address and replacing the stored first read length with the second read length when the subsequent read operation is not the reread operation.

16. The computer readable medium according to claim 12 further comprising:

storing a first time value for the previous read operation;

identifying a second time value for the subsequent read operation; and

invalidating the cache line when the count value is above the given threshold and a time difference between the first time value and the second time value is within a given time threshold.

17. The computer readable medium according to claim 16 further comprising replacing the stored first read start address with the second read start address, replacing the stored first read length with the second read length, clearing the count value, and updating the first time value with the second time value when the time difference between the first time value and the second time value is not within the given time threshold.