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Reduced latency memory read transactions in storage devices

  • US 8,959,307 B1
  • Filed: 11/13/2008
  • Issued: 02/17/2015
  • Est. Priority Date: 11/16/2007
  • Status: Active Grant
First Claim
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1. A storage apparatus for performing reduced memory read transactions, said storage apparatus responsive to memory transaction requests from at least one host, the storage apparatus comprising:

  • a memory array that includes a plurality of flash memory devices including a first flash memory device, said plurality of flash memory devices including a plurality of data registers, each one of said plurality of flash memory devices including a respective one of said plurality of data registers, said first flash memory device including a data register included in said plurality of data registers;

    said first flash memory device including a set of non-volatile memory cells and said data register;

    a memory interface coupled by a memory bus to said memory array;

    said memory interface coupled by a bus to the at least one host during a transmission of memory transaction requests from the at least one host to said memory interface;

    said memory interface including a Direct Memory Access (DMA) controller comprising a first buffer and a flash memory controller comprising a second buffer;

    a buffer set that includes a plurality of buffers that are suitable for use as prefetch buffers, said buffer set comprising said first buffer in said DMA controller in said memory interface and said second buffer in said flash memory controller in said memory interface;

    wherein said memory interface allocates a plurality of prefetch buffers in said buffer set, said plurality of prefetch buffers including said first buffer in said DMA controller and said second buffer in said flash memory controller so that said buffer set includes said plurality of prefetch buffers allocated for storing prefetch data and one or more non-allocated buffers available to said storage apparatus for other memory uses;

    wherein, in response to receiving a memory read transaction request, said memory interface performs a read operation, said memory interface configured to identify, within said memory array, stored data that meets a prefetch selection criterion and, if said memory interface identifies stored data existing within said memory array that meets a prefetch selection criterion, said memory interface performs an internal read operation that includes allocating said plurality of prefetch buffers in said buffer set and storing said stored data in at least one of said plurality of prefetch buffers as prefetch data; and

    wherein, if said memory interface receives a second memory read transaction request for data and if said data is currently available as said prefetch data in at least one of said plurality of prefetch buffers, said memory interface responds to said second memory read transaction request by performing a forwarding transaction that includes retrieving said prefetch data from at least one of said plurality of prefetch buffers and forwarding said prefetch data to a host, reducing read latency of said second memory read transaction request.

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