Reduced latency memory read transactions in storage devices
First Claim
1. A storage apparatus for performing reduced memory read transactions, said storage apparatus responsive to memory transaction requests from at least one host, the storage apparatus comprising:
- a memory array that includes a plurality of flash memory devices including a first flash memory device, said plurality of flash memory devices including a plurality of data registers, each one of said plurality of flash memory devices including a respective one of said plurality of data registers, said first flash memory device including a data register included in said plurality of data registers;
said first flash memory device including a set of non-volatile memory cells and said data register;
a memory interface coupled by a memory bus to said memory array;
said memory interface coupled by a bus to the at least one host during a transmission of memory transaction requests from the at least one host to said memory interface;
said memory interface including a Direct Memory Access (DMA) controller comprising a first buffer and a flash memory controller comprising a second buffer;
a buffer set that includes a plurality of buffers that are suitable for use as prefetch buffers, said buffer set comprising said first buffer in said DMA controller in said memory interface and said second buffer in said flash memory controller in said memory interface;
wherein said memory interface allocates a plurality of prefetch buffers in said buffer set, said plurality of prefetch buffers including said first buffer in said DMA controller and said second buffer in said flash memory controller so that said buffer set includes said plurality of prefetch buffers allocated for storing prefetch data and one or more non-allocated buffers available to said storage apparatus for other memory uses;
wherein, in response to receiving a memory read transaction request, said memory interface performs a read operation, said memory interface configured to identify, within said memory array, stored data that meets a prefetch selection criterion and, if said memory interface identifies stored data existing within said memory array that meets a prefetch selection criterion, said memory interface performs an internal read operation that includes allocating said plurality of prefetch buffers in said buffer set and storing said stored data in at least one of said plurality of prefetch buffers as prefetch data; and
wherein, if said memory interface receives a second memory read transaction request for data and if said data is currently available as said prefetch data in at least one of said plurality of prefetch buffers, said memory interface responds to said second memory read transaction request by performing a forwarding transaction that includes retrieving said prefetch data from at least one of said plurality of prefetch buffers and forwarding said prefetch data to a host, reducing read latency of said second memory read transaction request.
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Accused Products
Abstract
A solution for performing reduced latency memory read transactions is disclosed. In one example, a storage apparatus has a memory array that includes: a flash device having a data register, a memory interface coupled to the memory array and a buffer set that includes at least one buffer suitable for use as a prefetch buffer. The memory interface, in response to a memory read transaction request, performs a read operation and, if stored data exists within the memory array that meets a prefetch selection criterion, also performs an internal read operation. The internal read operation includes allocating a prefetch buffer in the buffer set and storing the data as prefetch data in the prefetch buffer. If the memory interface receives a second memory read transaction request for data that is currently available as prefetch data, the memory interface responds by performing a forwarding transaction that includes retrieving the prefetch data from the prefetch buffer and forwarding the prefetch data to a host.
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Citations
37 Claims
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1. A storage apparatus for performing reduced memory read transactions, said storage apparatus responsive to memory transaction requests from at least one host, the storage apparatus comprising:
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a memory array that includes a plurality of flash memory devices including a first flash memory device, said plurality of flash memory devices including a plurality of data registers, each one of said plurality of flash memory devices including a respective one of said plurality of data registers, said first flash memory device including a data register included in said plurality of data registers; said first flash memory device including a set of non-volatile memory cells and said data register; a memory interface coupled by a memory bus to said memory array; said memory interface coupled by a bus to the at least one host during a transmission of memory transaction requests from the at least one host to said memory interface; said memory interface including a Direct Memory Access (DMA) controller comprising a first buffer and a flash memory controller comprising a second buffer; a buffer set that includes a plurality of buffers that are suitable for use as prefetch buffers, said buffer set comprising said first buffer in said DMA controller in said memory interface and said second buffer in said flash memory controller in said memory interface; wherein said memory interface allocates a plurality of prefetch buffers in said buffer set, said plurality of prefetch buffers including said first buffer in said DMA controller and said second buffer in said flash memory controller so that said buffer set includes said plurality of prefetch buffers allocated for storing prefetch data and one or more non-allocated buffers available to said storage apparatus for other memory uses; wherein, in response to receiving a memory read transaction request, said memory interface performs a read operation, said memory interface configured to identify, within said memory array, stored data that meets a prefetch selection criterion and, if said memory interface identifies stored data existing within said memory array that meets a prefetch selection criterion, said memory interface performs an internal read operation that includes allocating said plurality of prefetch buffers in said buffer set and storing said stored data in at least one of said plurality of prefetch buffers as prefetch data; and wherein, if said memory interface receives a second memory read transaction request for data and if said data is currently available as said prefetch data in at least one of said plurality of prefetch buffers, said memory interface responds to said second memory read transaction request by performing a forwarding transaction that includes retrieving said prefetch data from at least one of said plurality of prefetch buffers and forwarding said prefetch data to a host, reducing read latency of said second memory read transaction request. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for reducing latency in memory read transactions by using a low latency memory interface coupled to a memory array that includes a plurality of flash memory devices including a flash memory device, wherein said plurality of flash memory devices includes a plurality of data registers, each one of said plurality of flash memory devices including a respective one of said plurality of data registers, and
wherein said memory interface responds to memory read transaction requests from a host, the method comprising: -
receiving a memory read transaction request; performing a read operation; identifying prefetch data in said memory array that meets a prefetch selection criterion; said memory interface coupled by a memory bus to said memory array; said memory interface coupled by a bus to the host during a transmission of memory transaction requests from the host to said memory interface; said memory interface including a Direct Memory Access (DMA) controller comprising a first buffer and a flash memory controller comprising a second buffer; if prefetch data is identified in said memory array, performing an internal read operation that includes transferring prefetch data, allocating said first buffer as a prefetch buffer suitable for storing prefetch data wherein said prefetch buffer is identified from at least one available buffer available in said buffer set that includes said first buffer in said DMA controller in said memory interface and said second buffer in said flash memory controller in said memory interface; said flash memory device including a set of non-volatile memory cells and said data register; said memory interface allocates a plurality of prefetch buffers in said buffer set, said plurality of prefetch buffers including said first buffer in said DMA controller and said second buffer in said flash memory controller so that said buffer set includes said plurality of prefetch buffers allocated for storing prefetch data and one or more non-allocated buffers available for other memory uses; storing said prefetch data in said at least one of said plurality of prefetch buffers; and performing a forwarding transaction if a second memory read transaction request is received for data stored as prefetch data. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A storage apparatus for performing reduced memory read transactions, the storage apparatus comprising:
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a memory array including a plurality of non-volatile memory devices; said plurality of non-volatile memory devices including a plurality of data registers, each one of said plurality of non-volatile memory devices including a respective one of said plurality of data registers; each of the non-volatile memory devices including a corresponding set of non-volatile memory cells and a respective data register; a memory interface coupled by a memory bus to the memory array and responsive to a memory read transaction request; said memory interface coupled by a bus to the at least one host during a transmission of memory transaction requests from the at least one host to said memory interface; said memory interface including a Direct Memory Access (DMA) controller comprising a first buffer and a flash memory controller comprising a second buffer; and wherein said memory interface allocates a plurality of prefetch buffers in said buffer set, said plurality of prefetch buffers including said first buffer in said DMA controller and said second buffer in said flash memory controller so that said buffer set includes said plurality of prefetch buffers allocated for storing prefetch data and one or more non-allocated buffers available to said storage apparatus for other memory uses; the memory interface configured to perform a read operation on the memory array in response to a memory read transaction request and configured to perform an internal read operation if the memory interface identifies stored data, in the memory array, meeting a prefetch selection criterion; the internal read operation comprising the memory interface allocating a data store in the buffer set and storing the stored data in the data store as a prefetch data available to a second memory read transaction. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A method of performing reduced memory read transactions in a storage apparatus, method comprising:
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receiving a memory read transaction request and performing a read operation on a memory array; and performing an internal read operation if stored data, in the memory array, meets a prefetch selection criterion; wherein performing the internal read operation comprises; allocating a data store in a buffer set formed in a memory interface and storing the stored data in the data store as a prefetch data available to a second memory read transaction; said memory array including a plurality of non-volatile memory devices, said plurality of non-volatile memory devices including a plurality of data registers, each one of said plurality of non-volatile memory devices including a respective one of said plurality of data registers; each of said non-volatile memory device including a corresponding set of non-volatile memory cells and a respective data register; and said memory interface coupled by a bus to the at least one host during a transmission of memory transaction requests from the at least one host to said memory interface; said memory interface including a Direct Memory Access (DMA) controller comprising a first buffer and a flash memory controller comprising a second buffer; wherein said memory interface, coupled by a memory bus to said memory array, allocates a plurality of prefetch buffers in said buffer set, said plurality of prefetch buffers including said first buffer in said DMA controller said memory interface and said second buffer in said flash memory controller in said memory interface so that said buffer set includes said plurality of prefetch buffers allocated for storing prefetch data and one or more non-allocated buffers available to said storage apparatus for other memory uses. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31)
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32. A method for reducing latency in memory read transactions by using a low latency memory interface coupled to a memory array that includes a flash memory device, and wherein said memory interface responds to memory read transaction requests from a host, the method comprising:
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receiving a memory read transaction request; performing a read operation; identifying prefetch data in said memory array that meets a prefetch selection criterion; said memory interface coupled by a memory bus to said memory array; said memory interface coupled by a bus to the host during a transmission of memory transaction requests from the host to said memory interface; said memory interface including a Direct Memory Access (DMA) controller comprising a first buffer and a flash memory controller comprising a second buffer; if prefetch data is identified in said memory array, performing an internal read operation that includes transferring prefetch data, allocating said first buffer as a prefetch buffer suitable for storing prefetch data wherein said prefetch buffer is identified from at least one available buffer available in said buffer set that includes said first buffer in said DMA controller in said memory interface and said second buffer in said flash memory controller in said memory interface; said flash memory device including a set of non-volatile memory cells and the data register; storing said prefetch data in said first buffer; and performing a forwarding transaction if a second memory read transaction request is received for data stored as prefetch data. - View Dependent Claims (33, 34, 35, 36, 37)
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Specification