Hardware automatic performance state transitions in system on processor sleep and wake events

• US 8,959,369 B2
• Filed: 01/08/2014
• Issued: 02/17/2015
• Est. Priority Date: 04/07/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: de Cesare, Josh P., Cho, Jung Wook, Takayanagi, Toshinari, Millet, Timothy J.
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US14/149,922
• Publication Number:
  US 20140122908A1
• Time in Patent Office: 405 Days
• Field of Search: 713/300, 713/320, 713/323, 713/324, 345/52, 365/227, 455/574
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Claims

1. A non-transitory computer accessible storage medium storing:

a plurality of drivers, each of the plurality of drivers corresponding to a respective component of a plurality of components of a system, wherein the plurality of drivers each comprise instructions which, when executed by a processor on the system, control the respective component; and

a power management unit driver comprising instructions which, when executed by the processor, control a power management unit in the system, wherein the power management unit driver is configured to program a plurality of configuration registers in the power management unit with data indicating one or more performance states for each performance domain of a plurality of performance domains in the system, and wherein each of the plurality of components is included in one of the plurality of performance domains; and

wherein a first driver of the plurality of drivers is configured to request activation of a first component of the plurality of components, and wherein the power management unit driver is configured to determine if one or more performance domains are to be changed responsive to the activation and to program one or more of the plurality of configuration registers responsive to the request from the first driver if the one or more performance domains are to be changed.

2. The non-transitory computer accessible storage medium as recited in claim 1 wherein the first driver is configured to request deactivation of the first component, and wherein the power management unit driver is configured to program one or more of the plurality of configuration registers responsive to the request and determining that the deactivation causes a change in one or more performance domains.

3. The non-transitory computer accessible storage medium as recited in claim 2 wherein the plurality of drivers are further configured to communicate events other than the activation and deactivation requests to the power management unit driver.

4. The non-transitory computer accessible storage medium as recited in claim 3 wherein the power management unit driver is configured to determine whether or not the communicated events result in a change to one or more of the performance domains, and wherein the power management unit driver is configured to program the plurality of configuration registers to effect the change.

5. The non-transitory computer accessible storage medium as recited in claim 2 wherein the power management unit driver is configured to maintain a device activity table identifying which of the plurality of components are active, and wherein the power management unit driver is configured to update the device activity table responsive to the requests from the plurality of drivers.

6. The non-transitory computer accessible storage medium as recited in claim 1 wherein the power management unit further comprises a second plurality of configuration registers, and the power management unit driver is configured to program the second plurality of configuration registers with pointers to the plurality of configuration registers to select the at least two performance states from performance states programmed into the plurality of configuration registers.

7. The non-transitory computer accessible storage medium as recited in claim 6 wherein changing the performance domains is effected by changing the second plurality of configuration registers to point to different ones of the plurality of configuration registers.

8. The non-transitory computer accessible storage medium as recited in claim 7 wherein each of the second plurality of configuration registers is assigned to a respective one of the plurality of performance domains and to one of the at least two performance states.

9. A system comprising:

a processor;

a plurality of components in a plurality of performance domains;

a power management unit coupled to the processor, the power management unit comprising a plurality of configuration registers programmable with data indicating one or more performance states for each performance domain of the plurality of performance domains; and

a non-transitory computer accessible storage medium coupled to the processor, the computer accessible storage medium storing;

a plurality of drivers, each of the plurality of drivers corresponding to a respective component of the plurality of components, wherein the plurality of drivers each comprise instructions which, when executed by the processor, control the respective component; and

a power management unit driver comprising instructions which, when executed by the processor, control the power management unit, wherein the power management unit driver is configured to program a plurality of configuration registers in the power management unit with data indicating one or more performance states for each performance domain of the plurality of performance domains; and

wherein the plurality of drivers are configured to interface to the power management unit driver to activate and deactivate the respective components, and wherein the power management unit driver is configured to control the performance states responsive to the activation and deactivation of components.

10. The system as recited in claim 9 wherein a first driver of the plurality of drivers corresponds to a first component of the plurality of components, and wherein the first driver is configured to request activation and deactivation of the first component from the power management unit driver, and wherein the power management unit driver is configured to selectively modify the performance states responsive to the request.

11. The system as recited in claim 9 wherein the plurality of drivers are further configured to communicate events other than the activation and deactivation requests to the power management unit driver.

12. The system as recited in claim 11 wherein the power management unit driver is configured to determine whether or not the communicated events result in a change to one or more performance states in one or more of the performance domains, and wherein the power management unit driver is configured to control the performance states responsive to determining that the communicated events result in the change.

13. The system as recited in claim 9 wherein the power management unit driver is configured to maintain a device activity table identifying which of the plurality of components are active, and wherein the power management unit driver is configured to update the device activity table responsive to the requests from the plurality of drivers.

14. The system as recited in claim 9 wherein the power management unit further comprises a second plurality of configuration registers, and the power management unit driver is configured to program the second plurality of configuration registers with pointers to the plurality of configuration registers to select the at least two performance states from performance states programmed into the plurality of configuration registers.

15. The system as recited in claim 14 wherein each of the second plurality of configuration registers is assigned to a respective one of the plurality of performance domains and to one of the at least two performance states.

16. A method, in a system including a processor;

a plurality of components in a plurality of performance domains; and

a power management unit coupled to the processor, the power management unit comprising a plurality of configuration registers programmable with data indicating one or more performance states for each performance domain of the plurality of performance domains;

the method comprising;

executing a first driver of a plurality of drivers on the processor, wherein each of the plurality of drivers corresponds to a respective component of the plurality of components, wherein the plurality of drivers each comprise instructions which, when executed by the processor, control the respective component; and

executing a power management unit driver on the processor, wherein the power management unit driver is configured to control the power management unit, and wherein the power management unit driver is configured to program a plurality of configuration registers in the power management unit with data indicating one or more performance states for each performance domain of the plurality of performance domains; and

responsive to a request to activate or deactivate a first component from a first driver of the plurality of drivers, the performance management unit driver controlling the performance states.

17. The method as recited in claim 16 further comprising:

the plurality of drivers, during execution, communicating events other than the activation and deactivation requests to the power management unit driver;

the power management unit driver, during execution, determining that the communicated events result in a change to one or more performance states in one or more of the performance domains; and

the power management unit driver, during execution, controlling the performance states responsive to the determining.

18. The method as recited in claim 16 further comprising:

the power management unit driver, during execution, maintaining a device activity table identifying which of the plurality of components are active; and

the power management unit driver, during execution, updating the device activity table responsive to the requests from the plurality of drivers.

19. The method as recited in claim 16 wherein the power management unit further comprises a second plurality of configuration registers, and the method further comprising the power management unit driver programming the second plurality of configuration registers with pointers to the plurality of configuration registers to select the at least two performance states from performance states programmed into the plurality of configuration registers.

20. The method as recited in claim 19 wherein each of the second plurality of configuration registers is assigned to a respective one of the plurality of performance domains and to one of the at least two performance states.