Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

• US 8,962,412 B2
• Filed: 08/11/2014
• Issued: 02/24/2015
• Est. Priority Date: 01/06/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Khakifirooz, Ali, Kerber, Pranita, Lavoie, Christian
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US14/456,199
• Publication Number:
  US 20140349459A1
• Time in Patent Office: 197 Days
• Field of Search: 438/197, 438/585, 438/300, 438/592
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.

Claims

1. A method to fabricate a transistor device, comprising:

depositing raised source drain structures adjacent to a gate stack disposed on a surface of a semiconductor material;

depositing metal on a top surface of each raised source drain structure and over a top surface of a gate conductor;

siliciding the deposited metal;

depositing a layer of field dielectric over the gate stack and the raised source drain structures;

opening apertures through the layer of field dielectric at contact locations, the apertures extending to the silicided metal at the top of each raised source drain structure;

forming a trench through the silicided metal at the top of each raised source drain structure, each trench extending at least partially into the raised source drain structure;

depositing metal to cover sidewalls and a bottom of at least a portion of each trench;

siliciding the deposited metal covering the sidewalls and the bottom of each trench; and

depositing contact metal into the apertures in electrically conductive contact with the silicided metal at the bottom of each trench and the silicided trench sidewalls;

where the contact metal is deposited to have one of tensile stress or compressive stress and where the layer of field dielectric is deposited to have tensile stress when the contact metal is deposited to have tensile stress, and where the layer of field dielectric is deposited to have compressive stress when the contact metal is deposited to have compressive stress.

2. The method of claim 1, performed when at least one of fabricating both N-type field effect transistors and P-type field effect transistors, or performed only for N-type field effect transistors and not P-type field effect transistors, or performed only for P-type field effect transistors and not N-type field effect transistors, or performed when fabricating both logic field effect transistors and memory field effect transistors, or performed only for logic field effect transistors and not memory field effect transistors, or performed only for memory field effect transistors and not logic field effect transistors.

3. The method of claim 1, where the surface of the semiconductor material is a surface of a silicon-on-insulator layer disposed over a layer of buried oxide, or is a surface of a bulk silicon substrate.

4. The method of claim 1, where opening apertures through the layer of field dielectric comprises etching.

5. The method of claim 4, where the etching comprises RIE.

6. The method of claim 5, where the etching further comprises sputtering to remove the silicided deposited metal on the top surface of each raised source drain structure and over the top surface of the gate conductor.

7. The method of claim 6, where the etching and sputtering are carried out in separate chambers.

8. The method of claim 4, where a tool used for etching by RIE comprises a sputtering capability.

9. The method of claim 1, where opening apertures through the layer of field dielectric comprises etching into the silicided deposited metal on the top surface of each raised source drain structure and over the top surface of the gate conductor.

10. The method of claim 1, where opening apertures through the layer of field dielectric comprises etching through the silicided deposited metal on the top surface of each raised source drain structure and over the top surface of the gate conductor and etching into the deposited raised source drain structure.

11. The method of claim 1, where opening apertures through the layer of field dielectric comprises etching through the silicided deposited metal on the top surface of each raised source drain structure and over the top surface of the gate conductor, through the deposited raised source drain structure, and into a silicon-on-insulator layer.

12. The method of claim 1, where opening apertures through the layer of field dielectric comprises etching through the silicided deposited metal on the top surface of each raised source drain structure and over the top surface of the gate conductor, through the deposited raised source drain structure, through a silicon-on-insulator layer, and to a layer of buried oxide on the surface of the semiconductor material.

13. The method of claim 1, where depositing metal to cover sidewalls and a bottom of at least a portion of each trench is followed by annealing.

14. The method of claim 13, where the annealing is carried out at a temperature of less than about 450 degrees C.

15. The method of claim 13, where the annealing produces NiSi, PtSi, or TiSi within the deposited raised source drain structures.

16. The method of claim 15, where the NiSi, PtSi, or TiSi within the deposited raised source drain structures is electrically contiguous with the silicided deposited metal on the top surface of the raised source drain structure.