N-type silicon solar cell with contact/protection structures

• US 8,962,424 B2
• Filed: 03/03/2011
• Issued: 02/24/2015
• Est. Priority Date: 03/03/2011
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Xu, Baomin
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US13/040,098
• Publication Number:
  US 20120222735A1
• Time in Patent Office: 1,454 Days
• Field of Search: 438/57, 438/66, 438/98, 136/244, 136/256
• US Class Current: 438/257
• CPC Class Codes: H01L 31/02167 for solar cells
• CPC Class Codes: H01L 31/022425 for solar cells
• CPC Class Codes: H01L 31/02245 for metallisation wrap-through [MWT] type solar cells
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

A solar cell is formed on an n-type semiconductor substrate having a p+ emitter layer by forming spaced-apart contact/protection structures on the emitter layer, depositing a blanket dielectric passivation layer over the substrate'"'"'s upper surface, utilizing laser ablation to form contact openings through the dielectric layer that expose corresponding contact/protection structures, and then forming metal gridlines on the upper surface of the dielectric layer that are electrically connected to the contact structures by way of metal via structures extending through associated contact openings. The contact/protection structures serve both as protection against substrate damage during the contact opening formation process (i.e., to prevent damage of the p+ emitter layer caused by the required high energy laser pulses), and also serve as optional silicide sources that facilitate optimal contact between the metal gridlines and the p+ emitter layer.

Claims

1. A method for fabricating an electrical circuit formed on a silicon substrate having an upper surface, the method comprising:

depositing spaced-apart contact structures on the upper surface of the silicon substrate;

depositing a blanket dielectric passivation layer over the contact structures and remaining exposed portions of the upper surface;

forming contact openings through the dielectric layer such that each contact opening exposes a portion of a corresponding contact structure;

forming metal gridlines on the upper surface of the dielectric layer such that each metal gridline is electrically connected to the silicon substrate by way of at least one via structure, wherein said at least one via structure extends through an associated contact opening of said plurality of contact openings,

wherein depositing the spaced-apart contact structures comprises selectively ejecting a metal-bearing ink from an ink jet printer.

2. A method for fabricating an electrical circuit formed on a silicon substrate having an upper surface, the method comprising:

depositing spaced-apart contact structures on the upper surface of the silicon substrate;

depositing a blanket dielectric passivation layer over the contact structures and remaining exposed portions of the upper surface;

forming contact openings through the dielectric layer such that each contact opening exposes a portion of a corresponding contact structure;

forming metal gridlines on the upper surface of the dielectric layer such that each metal gridline is electrically connected to the silicon substrate by way of at least one via structure, wherein said at least one via structure extends through an associated contact opening of said plurality of contact openings,

wherein depositing the spaced-apart contact structures comprises depositing an acceptor metal on the first portions of the upper surface, and then depositing a suicide-forming metal on the acceptor metal.

3. The method of claim 2 wherein depositing the spaced-apart contact structures comprises depositing said metal-bearing ink such that said metal-bearing ink forms on the upper surface one of a plurality of spaced-apart continuous line-structures, a plurality of spaced-apart dot-structures, and a plurality of spaced dashed-line structures.

4. A method for fabricating an electrical circuit formed on a silicon substrate having an upper surface, the method comprising:

depositing spaced-apart contact structures on the upper surface of the silicon substrate;

depositing a blanket dielectric passivation layer over the contact structures and remaining exposed portions of the upper surface;

forming contact openings through the dielectric layer such that each contact opening exposes a portion of a corresponding contact structure;

forming metal gridlines on the upper surface of the dielectric layer such that each metal gridline is electrically connected to the silicon substrate by way of at least one via structure, wherein said at least one via structure extends through an associated contact opening of said plurality of contact openings,

wherein the semiconductor substrate comprises an n-type body layer and a p+emitter layer disposed between the upper surface and the n-type body layer, and

wherein depositing the blanket dielectric passivation layer comprises depositing Al₂O₃ on the upper surface of the n-type semiconductor substrate using an atomic layer deposition (ALD) process.

5. The method of claim 4 wherein forming said contact openings comprises using a laser to ablate selected portions of said Al₂O₃ passivation layer.

6. A method for fabricating an electrical circuit formed on a silicon substrate having an upper surface, the method comprising:

depositing spaced-apart contact structures on the upper surface of the silicon substrate;

depositing a blanket dielectric passivation layer over the contact structures and remaining exposed portions of the upper surface;

forming contact openings through the dielectric layer such that each contact opening exposes a portion of a corresponding contact structure;

forming gridlines on the upper surface of the dielectric layer such that each metal gridline is electrically connected to the silicon substrate by way of at least one via structure, wherein said at least one via structure extends through an associated contact opening of said plurality of contact openings,

wherein forming the metal gridlines comprises depositing metal gridline material using one of an inkjet printing process, a screen printing process and a co-extrusion process, and then performing a firing process.

7. A method for fabricating an electrical circuit formed on a silicon substrate having an upper surface, the method comprising:

depositing spaced-apart contact structures on the upper surface of the silicon substrate;

depositing a blanket dielectric passivation layer over the contact structures and remaining exposed portions of the upper surface;

forming contact openings through the dielectric layer such that each contact opening exposes a portion of a corresponding contact structure;

forming metal gridlines on the upper surface of the dielectric layer such that each metal gridline is electrically connected to the silicon substrate by way of at least one via structure, wherein said at least one via structure extends through an associated contact opening of said plurality of contact openings,

further comprising forming a metal silicide structure at a junction formed by each of the via structures and said upper surface.

8. A method for fabricating an electrical circuit formed on a silicon substrate having an upper surface, the method comprising:

depositing spaced-apart contact structures on the upper surface of the silicon substrate;

depositing a blanket dielectric passivation layer over the contact structures and remaining exposed portions of the upper surface;

forming contact openings through the dielectric layer such that each contact opening exposes a portion of a corresponding contact structure;

forming metal gridlines on the upper surface of the dielectric layer such that each metal gridline is electrically connected to the silicon substrate by way of at least one via structure, wherein said at least one via structure extends through an associated contact opening of said plurality of contact openings,

further comprising forming a selective emitter layer structure wherein first emitter layer regions underlying each said contact structure have smaller sheet resistances than sheet resistances of second emitter layer regions disposed between the contact structures.