Method for fabricating capacitor with high aspect ratio

• US 8,962,437 B2
• Filed: 06/12/2012
• Issued: 02/24/2015
• Est. Priority Date: 03/19/2012
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Beom-Yong, Lee, Kee-Jeung, Ji, Yun-Hyuck, Lee, Seung-Mi, Koo, Jae-Hyoung, Do, Kwan-Woo, Park, Kyung-Woong, Ahn, Ji-Hoon, Park, Woo-Young
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): PATERSON, BRIGITTE A
• Application Number:
  US13/494,400
• Publication Number:
  US 20130244394A1
• Time in Patent Office: 987 Days
• Field of Search: 438/381
• US Class Current: 438/381
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer.

Claims

1. A method for fabricating a capacitor, comprising:

forming an etch stop layer over a semiconductor substrate having a storage node contact plug formed therein;

forming a first silicon layer over the etch stop layer, wherein the first silicon layer is doped with a dopant;

forming an undoped second silicon layer over the first silicon layer;

forming an opening by etching the second silicon layer and the first silicon layer;

forming a silicon oxide layer on sidewalls of the opening by oxidizing the first silicon layer and the second silicon layer;

expanding the opening by removing the silicon oxide layer;

etching the etch stop layer under the expanded opening;

forming a storage node in the expanded opening; and

removing the first silicon layer and the second silicon layer,

wherein the first and second silicon layers comprise amorphous silicon and are heat-treated during a subsequent process.

2. The method of claim 1, wherein the first and second silicon layers comprise amorphous silicon.

3. The method of claim 1, wherein the dopant doped in the first silicon layer comprises boron or phosphorous.

4. The method of claim 1, wherein the doping concentration of the dopant doped in the first silicon layer is in the range of 1×

10¹⁸ to 1×

10²² atoms/cm³.

5. The method of claim 1, wherein, in the forming of the first silicon layer, the dopant is insitu-doped when the first silicon layer is deposited.

6. The method of claim 1, wherein the forming of the silicon oxide layer is performed by a process selected from plasma oxidation, thermal oxidation, in-situ steam generation (ISSG), water vapor generation (WVG), and radical oxidation.