ESD network circuit with a through wafer via structure and a method of manufacture

• US 8,962,480 B2
• Filed: 06/04/2012
• Issued: 02/24/2015
• Est. Priority Date: 03/26/2009
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven H.
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US13/487,904
• Publication Number:
  US 20120238069A1
• Time in Patent Office: 995 Days
• Field of Search: None
• US Class Current: 438/667
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A method includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate.

Claims

1. A method comprising:

forming an ESD active device on a substrate and electrically connected between an input and at least one power rail;

forming a ground plane on a backside of the substrate, wherein the ground plane is formed on a bottom of the substrate;

forming at least one through wafer via structure to provide a low series resistance path to the substrate, wherein the at least one through wafer via structure is in contact with a negative power supply; and

forming at least one additional through wafer via structure,

wherein both of the at least one through wafer via structure and the at least one additional through wafer via structure are in contact with the ground plane and provide a guard ring to prevent minority carrier migration.

2. The method of claim 1, further comprising forming at least one further through wafer via structure in contact with the ground plane and structured and arranged to lower a resistance of the ESD active device at least one of laterally and vertically.

3. A method comprising:

forming an ESD active device on a substrate and electrically connected between an input and at least one power rail;

forming at least one through wafer via structure to provide a low series resistance path to the substrate; and

forming a ground plane on a bottom of the substrate and electrically connected to the at least one through wafer structure,

wherein the at least one through wafer via structure is in contact with a negative power supply and the ground plane formed on the bottom of the substrate.

4. A method comprising:

forming an ESD active device on a substrate and electrically connected between an input and at least one power rail;

forming at least one through wafer via structure to provide a low series resistance path to the substrate;

forming at least one inductor electrically connected to the at least one through wafer via structure through a connection with a VSS negative power supply;

providing an inductor shield between the at least one inductor and the at least one through wafer via structure;

etching one or more passages through the inductor shield; and

forming one or more vias within the one or more passages through the inductor shield to form the connection between the at least one inductor and the VSS negative power supply.