Trench-based power semiconductor devices with increased breakdown voltage characteristics

• US 8,963,212 B2
• Filed: 10/21/2013
• Issued: 02/24/2015
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Challa, Ashok, Kinzer, Daniel M., Probst, Dean E., Calafut, Daniel
• Primary Examiner(s): Sefer, A.
• Application Number:
  US14/058,954
• Publication Number:
  US 20140042532A1
• Time in Patent Office: 491 Days
• Field of Search: 257/170, 257/213, 257/330, 257/334
• US Class Current: 257/213
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

In one general aspsect, a semiconductor device can include at least a first device region and a second device region disposed at a surface of a semiconductor region where the second device region is adjacent to the first device region and spaced apart from the first device region. That semiconductor device can include a connection region disposed between the first device region and the second device region, and a trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region. The semiconductor device can include a dielectric layer lining opposing sidewalls of the trench, an electrode disposed in the trench, and a conductive trace disposed over a portion of the trench in the connection region and electrically coupled to a portion of the electrode disposed in the connection region.

Claims

1. A semiconductor device, comprising:

at least a first device region and a second device region disposed at a surface of a semiconductor region, the second device region being adjacent to the first device region and spaced apart from the first device region;

a connection region disposed between the first device region and the second device region;

a trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region;

a dielectric layer lining opposing sidewalls of the trench;

an electrode disposed in the trench; and

a conductive trace disposed over a portion of the trench in the connection region and electrically coupled to a portion of the electrode disposed in the connection region.

2. The semiconductor device of claim 1, wherein the electrode includes a gate electrode, and has a dielectric disposed over the electrode in each of the first device region and the second device region.

3. The semiconductor device of claim 1, wherein the electrode includes a shield electrode,

the semiconductor device further comprising:

a gate electrode disposed in the first trench but electrically insulated from the shield electrode.

4. The semiconductor device of claim 3, wherein the conductive trace is a first conductive trace,

the semiconductor device further comprising:

a second conductive trace disposed over the trench in the connection region and electrically coupled to the gate electrode in the connection region, and electrically insulated from the shield electrode.

5. The semiconductor device of claim 1, further comprising:

a mesa region disposed adjacent to the trench;

a first configuration of one or more material bodies with a portion of the mesa region within the connection region;

a second configuration of one or more material bodies with the portion of the mesa region within the first device region; and

a third configuration of one or more material bodies with the portion of the mesa region within the first device region, the first configuration being different from each of the second configuration and the third configuration.

6. The semiconductor device of claim 1, wherein the trench is first trench, the conductive trace is a first conductive trace,

the semiconductor device further comprising:

a second trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region; and

a well region of a first conductivity type disposed in the semiconductor region and between the first trench and the second trench, the well region having an end; and

a second conductive trace disposed over the first trench and the second trench, the second conductive trace having a length running perpendicular to the first trench and the second trench and having a width that is less than the length of the second conductive trace, the second conductive trace having a portion spaced from a portion of the semiconductor region disposed between the first trench and the second trench by a first distance, the portion of the second conductive trace having a first side and a second side parallel to the length of the second conductive trace, the first side being closer than the second side to the end of the well region, the end of the well region being spaced from the second side of the second conductive trace by at least a second distance.

7. The semiconductor device of claim 6, wherein the well region extends to a depth into the semiconductor region, the second distance is equal to the depth.

8. The semiconductor device of claim 6, wherein the well region extends to a depth into the semiconductor region, the second distance is equal to the first distance plus the depth.

9. The semiconductor device of claim 1, further comprising:

a well region adjacent the trench, the well region being electrically coupled to a conductive layer to receive a potential.

10. The semiconductor device of claim 1, wherein the trench is a first trench,

the semiconductor device further comprising:

a second trench extending into the semiconductor region;

a first well region of a first conductivity type disposed between the first trench and the second trench; and

a second well region of the first conductivity type disposed in the semiconductor region between the first trench and the second trench, and disposed under the conductive trace.

11. The semiconductor device of claim 10, wherein the second well region is electrically floating.

12. The semiconductor device of claim 1, further comprising a well region of a first conductivity type disposed in the semiconductor region and under the first conductive trace.

13. The semiconductor device of claim 12, wherein the well region is electrically floating.

14. The semiconductor device of claim 1, wherein the trench is a first trench,

the semiconductor device further comprising:

a second trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region; and

a well region of a first conductivity type disposed in the semiconductor region and between the first trench and the second trench, the well region extending from the first device region, through the connection region, and to the second device region.

15. A semiconductor device, comprising:

a plurality of trenches extending into a semiconductor region, a trench from the plurality of trenches having a first end, a second end, and opposing sidewalls lined with a dielectric layer, the trench further including a shield electrode and a gate electrode vertically stacked above and insulated from the shield electrode; and

a conductive shield trace disposed over the semiconductor region and aligned orthogonal to the trench, the conductive trace having a length running adjacent to the first end of the trench and a width that does not extend over the first end of the trench, the conductive shield trace in electrical contact with the shield electrode included in the trench.

16. The semiconductor device of claim 15, wherein the trench extends in a horizontal direction between the first end and the second end.

17. The semiconductor device of claim 15, further comprising:

a gate runner disposed over the trench and disposed horizontally between the conductive shield trace and a device region.

18. The semiconductor device of claim 15, further comprising:

a well region adjacent the trench, the well region being electrically coupled to a conductive layer to receive a potential or floating.

19. A semiconductor device, comprising:

a plurality of trenches extending into a semiconductor region, a trench from the plurality of trenches having a first end, a second end, and opposing sidewalls lined with a dielectric layer, the trench further including a shield electrode; and

a conductive shield trace disposed over the semiconductor region and aligned orthogonal to the trench, the conductive trace having a length running adjacent to the first end of the trench and a width extending over the first end of the trench, the conductive shield trace in electrical contact with the shield electrode included in the trench.

20. The semiconductor device of claim 19, wherein the semiconductor device comprises a trench-shield Schottky barrier diode.

21. The semiconductor device of claim 19, wherein the trench extends in a horizontal direction between the first end and the second end.

22. The semiconductor device of claim 19, further comprising:

a gate runner disposed over the trench and disposed horizontally between the conductive shield trace and a device region.

23. The semiconductor device of claim 19, further comprising:

a well region adjacent the trench, the well region being electrically coupled to a conductive layer to receive a potential or floating.