Thin film transistor, method of manufacturing the thin film transistor and organic light emitting display device have the thin film transistor

• US 8,963,214 B2
• Filed: 09/28/2010
• Issued: 02/24/2015
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Im, Ki-Ju, Park, Dong-Wook, Mo, Yeon-Gon, Kim, Hye-Dong, Kondratyuk, Roman
• Primary Examiner(s): Monbleau, Davienne
• Assistant Examiner(s): Cruz, Leslie Pilar
• Application Number:
  US12/892,820
• Publication Number:
  US 20110084262A1
• Time in Patent Office: 1,610 Days
• Field of Search: 257/250, 257/266, 257/270, 257/365, 257/366, 257/401, 257/E29.134, 257/E29.135, 257/E29.264, 257/E29.265, 257/E29.269, 257/43, 257/288, 257/E29.275, 257/E29.112, 257/E29.122, 257/E29.117, 257/E29.136, 257/E29.137, 257/E51.019, 257/E29.29, 257/E29.293
• US Class Current: 257/250
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A thin film transistor for an organic light emitting display device is disclosed. In one embodiment, the thin film transistor includes: a substrate, an active layer formed over the substrate, wherein the active layer is formed of an oxide semiconductor, a gate insulating layer formed over the substrate and the active layer, and source and drain electrodes formed on the gate insulating layer and electrically connected to the active layer. The transistor may further include a gate electrode formed on the gate insulating layer and formed between the source and drain electrodes, wherein the gate electrode is spaced apart from the source electrode so as to define a first offset region therebetween, and wherein the gate electrode is spaced apart from the drain electrode so as to define a second offset region therebetween. The transistor may further include a passivation layer formed on i) the gate insulating layer, ii) the source and drain electrodes and iii) the gate electrode; and at least one auxiliary gate electrode formed on the passivation layer, wherein at least a portion of the auxiliary gate electrode is located directly above the first and second offset regions.

Claims

1. A thin film transistor, comprising:

a substrate;

an active layer formed over the substrate, wherein the active layer is formed of an oxide semiconductor;

a gate insulating layer formed over the substrate and the active layer;

source and drain electrodes formed on the gate insulating layer and electrically connected to the active layer;

a gate electrode formed on the gate insulating layer and formed between the source and drain electrodes, wherein the gate electrode is spaced apart from the source electrode, wherein a first gap between the gate electrode and the source electrode is defined as a first offset region, wherein the gate electrode is spaced apart from the drain electrode, and wherein a second gap between the gate electrode and the drain electrode is defined as a second offset region;

a passivation layer formed on i) the gate insulating layer, ii) the source and drain electrodes and iii) the gate electrode; and

at least one auxiliary gate electrode formed on the passivation layer, wherein the auxiliary gate electrode comprises first and second auxiliary gate electrodes, wherein at least a portion of the first auxiliary gate electrode is located directly above the first offset region, wherein at least a portion of the second auxiliary gate electrode is located directly above the second offset region, and

wherein the first and second auxiliary gate electrodes are formed on the same layer.

2. The thin film transistor of claim 1, wherein the source and drain electrodes are electrically connected to the active layer through a contact hole formed on the gate insulating layer.

3. The thin film transistor of claim 1, wherein the oxide semiconductor contains zinco oxide (ZnO).

4. The thin film transistor of claim 3, wherein the oxide semiconductor comprises at least one ion of:

gallium (Ga), indium (In), stanium (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), magnesium (Mg), and vanadium (V).

5. The thin film transistor of claim 3, wherein the oxide semiconductor comprises at least one ion of:

1-group elements, 13-group elements, 14-group elements, 15-group elements, and 17-group elements.

6. The thin film transistor of claim 1, wherein the auxiliary gate electrode overlaps the first offset region and the second offset region in a direction substantially perpendicular to the substrate.

7. A thin film transistor, comprising:

a substrate;

source and drain electrodes formed over the substrate;

a gate electrode formed over the substrate and formed between the source and drain electrodes, wherein the gate electrode is spaced apart from the source electrode, wherein a first gap between the gate electrode and the source electrode is defined as a first offset region, wherein the gate electrode is spaced apart from the drain electrode, and wherein a second gap between the gate electrode and the drain electrode is defined as a second offset region;

a gate insulating layer covering the gate electrode;

an active layer formed on i) the gate insulating layer, ii) the source and drain electrodes and iii) at least part of the first and second offset regions;

a passivation layer formed on the active layer; and

at least one auxiliary gate electrode formed on the passivation layer, wherein at least a portion of the auxiliary gate electrode is located directly above the first offset region.

8. The thin film transistor of claim 7, wherein at least part of the auxiliary gate electrode overlaps with the gate electrode.

9. The thin film transistor of claim 7, wherein the at least one auxiliary gate electrode is a single piece electrode.

10. The thin film transistor of claim 7, wherein the source and drain electrodes and the gate electrode are made of the same material.

11. The thin film transistor of claim 7, wherein the active layer contains zinc oxide (ZnO).

12. A method of manufacturing a thin film transistor, comprising:

forming a semiconductor active layer over a substrate;

forming a gate insulating layer over the substrate and the active layer;

forming i) source and drain electrodes, electrically connected to the active layer, on the gate insulating layer and ii) a gate electrode between the source and drain electrodes, wherein the gate electrode is spaced apart from the source electrode, wherein a first gap between the gate electrode and the source electrode is defined as a first offset region, wherein the gate electrode is spaced apart from the drain electrode, and wherein a second gap between the gate electrode and the drain electrode is defined as a second offset region;

forming a passivation layer on i) the gate insulating layer, ii) the source and drain electrodes and iii) the gate electrode; and

forming at least one auxiliary gate electrode on the passivation layer, wherein the auxiliary gate electrode comprises first and second auxiliary gate electrodes, wherein at least a portion of the first auxiliary gate electrode is located directly above the first offset region, wherein at least a portion of the second auxiliary gate electrode is located directly above the second offset region, and

wherein the first and second auxiliary gate electrodes are formed on the same layer.

13. The method of claim 12, wherein the forming the source and drain electrodes, and the gate electrode comprises:

forming a contact hole on the gate insulating layer to expose a predetermined part of the active layer;

forming a conductive layer on the gate insulating layer to fill the contact hole; and

forming the source and drain electrodes and the gate electrode by patterning the conductive layer.

14. The method of claim 12, wherein at least a portion of the auxiliary gate electrode overlaps with the gate electrode.

15. The method of claim 12, wherein the auxiliary gate electrode overlaps the first offset region and the second offset region in a direction substantially perpendicular to the substrate.

16. An organic light emitting display device, comprising:

a first substrate;

a second substrate disposed to face the first substrate,

an organic light emitting device interposed between the first and second substrates, wherein the organic light emitting device comprises a first electrode, an organic light emitting layer, a second electrode and a thin film transistor configured to control an operation of the organic light emitting device; and

wherein the thin film transistor comprises;

a substrate;

an active layer formed over the substrate, wherein the active layer is formed of an oxide semiconductor;

a gate insulating layer formed over the substrate and the active layer;

source and drain electrodes formed on the gate insulating layer and electrically connected to the active layer;

a gate electrode formed on the gate insulating layer and formed between the source and drain electrodes, wherein the gate electrode is spaced apart from the source electrode, wherein a first gap between the gate electrode and the source electrode is defined as a first offset region, wherein the gate electrode is spaced apart from the drain electrode, and wherein a second gap between the gate electrode and the drain electrode is defined as a second offset region;

a passivation layer formed on i) the gate insulating layer, ii) the source and drain electrodes and iii) the gate electrode; and

at least one auxiliary gate electrode formed on the passivation layer, wherein the auxiliary gate electrode comprises first and second auxiliary gate electrodes, wherein at least a portion of the first auxiliary gate electrode is located directly above the first offset region, wherein at least a portion of the second auxiliary gate electrode is located directly above the second offset region, and

wherein the first and second auxiliary gate electrodes are formed on the same layer.

17. The organic light emitting display device of claim 16, wherein the source and drain electrodes are electrically connected to the active layer through a contact hole formed on the gate insulating layer.

18. The organic light emitting display device of claim 16, wherein at least part of the auxiliary gate electrode overlaps with the gate electrode.

19. The organic light emitting display device of claim 16, wherein the auxiliary gate electrode and the first electrode are made of the same material on the same plane.

20. The organic light emitting display device of claim 16, wherein the auxiliary gate electrode overlaps the first offset region and the second offset region in a direction substantially perpendicular to the substrate.