Wafer structure and power device using the same

• US 8,963,217 B2
• Filed: 02/03/2014
• Issued: 02/24/2015
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Liao, Zhongping
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US14/170,764
• Publication Number:
  US 20140252554A1
• Time in Patent Office: 386 Days
• Field of Search: 257/262, 257/263, 257/328, 257/329, 257/335, 438268-272, 438/316, 438/336
• US Class Current: 257/262
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

In one embodiment, a wafer structure configured for a power device can include: (i) a first doping layer having a high doping concentration; (ii) a second doping layer on the first doping layer, where a doping concentration of the second doping layer is less than the high doping concentration; and (iii) a third doping layer on the second doping layer, where a doping concentration of the third doping layer is greater than the doping concentration of the second doping layer. For example, the power device can be part of a switching voltage regulator.

Claims

1. A wafer structure configured for a power device, the wafer structure comprising:

a) a first doping layer having a high doping concentration;

b) a second doping layer on said first doping layer, wherein a doping concentration of said second doping layer is less than a doping concentration of said first doping layer, and wherein said first and second doping layers have a same dopant type;

c) a third doping layer on said second doping layer, wherein a doping concentration of said third doping layer is greater than said doping concentration of said second doping layer;

d) p-type regions in said third doping layer;

e) n-type source regions in said p-type regions;

f) polysilicon gates between said p-type regions and above said third doping layer; and

g) a metal layer for connection to said n-type source regions.

2. The wafer structure of claim 1, wherein said second doping layer is formed by epitaxial growth on said first doping layer.

3. The wafer structure of claim 1, wherein said third doping layer is formed by epitaxial growth on said second doping layer.

4. The wafer structure of claim 1, wherein said third doping layer is formed by ion injection into a surface of said second doping layer.

5. The wafer structure of claim 1, wherein said first doping layer, said second doping layer, and said third doping layer each have a same dopant material.

6. The wafer structure of claim 1, wherein said doping concentration of said second doping layer is uniformly distributed.

7. The wafer structure of claim 1, wherein said doping concentration of said third doping layer is uniformly distributed.

8. The wafer structure of claim 1, wherein said doping concentration of said third doping layer is gradiently distributed.

9. A switching voltage regulator, comprising:

a) said wafer structure of claim 1; and

b) said power device formed in said wafer structure.

10. The switching voltage regulator of claim 9, wherein said power device comprises a metal oxide semiconductor field-effect transistor (MOSFET).

11. The switching voltage regulator of claim 10, wherein said MOSFET comprises a longitude super-junction metal oxide field-effect transistor or a vertical double diffused metal oxide semiconductor field-effect transistor (VDMOS).

12. The switching voltage regulator of claim 9, wherein said power device comprises an insulated gate bipolar transistor (IGBT).

13. The switching voltage regulator of claim 9, wherein said power device comprises a diode.

14. A method of making a VDMOS transistor in a wafer, the method comprising:

a) forming a first doping layer having a high doping concentration;

b) forming a second doping layer on said first doping layer, wherein a doping concentration of said second doping layer is less than a doping concentration of said first doping layer, and wherein said first and second doping layers have a same dopant type;

c) forming a third doping layer on said second doping layer, wherein a doping concentration of said third doping layer is greater than said doping concentration of said second doping layer;

d) forming p-type regions in said third doping layer;

e) forming n-type source regions in said p-type regions;

f) forming polysilicon gates between said p-type regions and above said third doping layer; and

g) forming a metal layer for connection to said n-type source regions.

15. The method of claim 14, wherein said forming said first doping layer comprises heavily doping a silicon substrate with n-type impurities.

16. The method of claim 14, wherein said forming said second doping layer comprises lightly doping said second doping layer with n-type impurities.

17. The method of claim 14, further comprising forming a thin an oxide layer prior to forming said polysilicon gates.

18. The method of claim 14, further comprising forming an oxide layer on said polysilicon gates.