Shielded gate trench (SGT) mosfet devices and manufacturing processes

• US 8,963,240 B2
• Filed: 04/26/2013
• Issued: 02/24/2015
• Est. Priority Date: 04/26/2013
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Lui, Sik K.
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US13/870,993
• Publication Number:
  US 20140319606A1
• Time in Patent Office: 669 Days
• Field of Search: 257/334, 257/340, 257/341, 257/355, 257/386, 257/E27.06, 257/E29.18, 257/E21.575, 257/E21.629, 438/268
• US Class Current: 257/340
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.

Claims

1. A semiconductor power device comprising a plurality of power transistor cells surrounded by trenches opened in a semiconductor substrate wherein:

each of said transistor cells having a source region encompassed in a body region disposed next to a trenched gate with a gate material filling in the trenches surrounding said transistor cell wherein said trenched gate further having a bottom-shielding electrode filled with the gate material disposed below and insulated from an upper gate segment said trenched gate electrically connected to a gate pad and wherein the transistor cells further surrounding an intersection of two trenches constituting a source contacting trench with the gate filling material filling an entire vertical length of the intersection of the two trenches and electrically connected to the bottom-shield electrode for electrically connected to a source metal covering over the intersection; and

a deep body-dopant region in a termination area to function as a guard ring or a Junction-termination extension type termination.

2. The semiconductor power device of claim 1 wherein:

said transistor cells having a macro cell layout with each of the transistor cells configured as a square cell surrounded by said trenches.

3. The trenched power semiconductor power device of claim 2 further comprising:

an insulation protective layer disposed on top of said semiconductor power device having a plurality of source openings disposed on top of said source region and on top of the intersection of the two trenches functioning as said source connecting trench provided for electrically connecting to said source metal.

4. The semiconductor power device of claim 1 further comprising:

an insulation protective layer disposed on top of said semiconductor power device having a gate pad opening provided for covering by the gate pad for electrically connecting said gate pad to said trenched gate.

5. The semiconductor power device of claim 4 wherein:

said gate opening is disposed directly above a gate runner trench laterally extended from the trenches to a termination area of said semiconductor power device.

6. The semiconductor power device of claim 5 wherein

said gate runner trench is wider and deeper than said trenches surrounding the transistor cells provided for forming said trenched gate therein.

7. The semiconductor power device of claim 5 wherein:

said gate runner trench is also filled with the gate material as the upper gate segment disposed in an upper portion of the gate runner trench and further includes and insulated from said bottom-shielding electrode.

8. The semiconductor power device of claim 1 wherein:

said deep body-dopant region is deeper than and encompassing said gate runner trench in said termination area.

9. The semiconductor power device of claim 1 further comprising:

a drain electrode disposed on a bottom surface of said semiconductor substrate.

10. The semiconductor power device of claim 1 wherein:

the body region of each of said transistor cells further extends between said trenches surrounding said transistor cells.

11. The semiconductor power device of claim 1 wherein said body region disposed next to said trenched gate and extends vertically in the semiconductor substrate to a depth about a bottom of the upper gate segment.

12. The semiconductor power device of claim 1 wherein:

an oxide layer is disposed above said bottom-shielding electrode to shield and insulate said bottom-shielding electrode from the upper gate segment of said trenched gate.

13. The semiconductor power device of claim 1 wherein:

an oxide layer is disposed above said bottom-shielding electrode to shield and insulate said bottom-shielding electrode from said the upper gate segment of trenched gate wherein said oxide layer above said bottom-shielding electrode is disposed in said trench with a predefined depth controlled by a timed etch process.

14. The semiconductor power device of claim 13 wherein:

said semiconductor power device having a reduced gate to drain capacitance Cgd depending on a depth of said oxide layer and a height of said bottom-shielding electrode.

15. The semiconductor power device of claim 1 wherein:

said bottom-shielding electrode filled with said gate material having a stepwise tapered profile toward a bottom of said trenches with a lining layer surrounded said gate material having a correspondingly stepwise increased thickness.

16. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising trenched metal oxide semiconductor field effect transistor (MOSFET) cells.