Semiconductor device and method for manufacturing semiconductor device

• US 8,963,246 B2
• Filed: 03/09/2011
• Issued: 02/24/2015
• Est. Priority Date: 03/09/2010
• Status: Active Grant

• Current Assignee: Inter-University Research Institute Corporation High Energy Accelerator Research Organization, LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: Inter-University Research Institute Corporation High Energy Accelerator Research Organization, LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Arai, Yasuo, Okihara, Masao, Kasai, Hiroki
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US13/583,409
• Publication Number:
  US 20130043537A1
• Time in Patent Office: 1,448 Days
• Field of Search: 257/347, 257/E27.112, 257/E21.409, 257/E29.255, 438/311, 438/328
• US Class Current: 257/347
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Claims

1. A semiconductor device that serves as a sensor formed on an SOI substrate for X-ray detection, comprising:

the SOI substrate including

a second-conductive-type semiconductor layer having first and second regions each being on one surface of the second-conductive-type semiconductor layer, the first and second regions being adjacent each other on the one surface of the second-conductive-type semiconductor layer,

an oxide film layer having one surface contacting the one surface of the second-conductive-type semiconductor layer, and

a first-conductive-type semiconductor layer having one surface contacting another surface of the oxide film layer that is opposite the one surface of the oxide film layer;

a first first-conductive-type diffusion layer is formed in the first region of the second-conductive-type semiconductor layer and in direct contact with the one surface of the second-conductive-type semiconductor layer;

a second first-conductive-type diffusion layer, with a higher impurity concentration than that in the first first-conductive-type diffusion layer, formed in a portion of the first first-conductive-type diffusion layer and in direct contact with the one surface of the second-conductive-type semiconductor layer;

a diode including a first second-conductive-type diffusion layer and a third first-conductive-type diffusion layer with a high impurity concentration formed at a portion of the second region, the diode being in direct contact with the one surface of the second-conductive-type semiconductor layer;

a MOS-type transistor formed in a region of the first region that includes another surface of the first-conductive-type semiconductor layer opposite to the one surface of the first-conductive-type semiconductor layer;

a first electrode that passes through the oxide film layer and is connected to the second first-conductive-type diffusion layer;

a second electrode that passes through the oxide film layer and is connected to the first second-conductive-type diffusion layer; and

a third electrode that passes through the oxide film layer and is connected to the third first-conductive-type diffusion layer.

2. The semiconductor device according to claim 1, further comprising a voltage applying unit for applying voltage to

an other surface of the second-conductive-type semiconductor layer opposite to the one surface of the second-conductive-type semiconductor layer, and

the second electrode,

wherein the first electrode and the third electrode are connected to ground.

3. The semiconductor device according to claim 1, further comprising:

a second second-conductive-type diffusion layer formed in the first first-conductive-type diffusion layer so as to be in contact with the oxide film layer;

a third second-conductive-type diffusion layer with a higher impurity concentration than that in the second second-conductive-type diffusion layer and being formed in a portion of the second second-conductive-type diffusion layer; and

a fourth electrode that passes through the oxide film layer and is connected to the third second-conductive-type diffusion layer.

4. The semiconductor device according to claim 3, further comprising

a voltage applying unit for applying voltage to

another surface of the second-conductive-type semiconductor layer opposite to the one surface of the second-conductive-type semiconductor layer, and

the second electrode,

wherein the first electrode, the third electrode and the fourth electrode are connected to ground.