Voltage regulator circuit comprising transistor which includes an oixide semiconductor

• US 8,963,517 B2
• Filed: 10/21/2010
• Issued: 02/24/2015
• Est. Priority Date: 10/21/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Miyake, Hiroyuki, Tsubuku, Masashi, Noda, Kosei
• Primary Examiner(s): Pham, Emily P
• Application Number:
  US12/909,556
• Publication Number:
  US 20110089927A1
• Time in Patent Office: 1,587 Days
• Field of Search: 323/222, 323/223, 323/226, 323/271
• US Class Current: 323/271
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

A transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, and an oxide semiconductor layer whose carrier concentration is 5×10¹⁴/cm³ or less is used for a channel formation layer. A capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal which is output as an output signal through the other of the source and the drain of the transistor.

Claims

1. A voltage regulator circuit comprising:

a transistor including a gate, a source, and a drain, wherein the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, an oxide semiconductor layer is used for a channel formation layer, and an off current is less than or equal to 100 zA/μ

m; and

a capacitor including a first electrode and a second electrode, wherein the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode,

wherein a voltage of the first signal is stepped up or down to obtain a third signal, and the third signal which has a voltage obtained by stepping up or down the voltage of the first signal is output as an output signal through the other of the source and the drain of the transistor.

2. The voltage regulator circuit according to claim 1, wherein the off current of the transistor is less than or equal to 10 zA/μ

m.

3. The voltage regulator circuit according to claim 1, wherein a carrier concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁴/cm³.

4. A voltage regulator circuit comprising n stages (n is a natural number of greater than or equal to 2) of unit step-up circuits which are electrically connected to each other in series, comprising:

a unit step-up circuit of a (2M−

1)-th stage (M is any one of 1 to n/2, and 2M is a natural number) comprising;

a first transistor including a gate, a source, and a drain, wherein the gate is electrically connected to one of the source and the drain, an oxide semiconductor layer of the first transistor is used for a channel formation layer, and an off current of the first transistor is less than or equal to 100 zA/μ

m, and

a first capacitor including a first electrode and a second electrode, wherein the first electrode is electrically connected to the other of the source and the drain of the first transistor, and a clock signal is input to the second electrode; and

a unit step-up circuit of a 2M-th stage comprising;

a second transistor including a gate, a source, and a drain, wherein the gate is electrically connected to one of the source and the drain, an oxide semiconductor layer of the second transistor is used for a channel formation layer, and an off current of the second transistor is less than or equal to 100 zAμ

m, and

a second capacitor including a first electrode and a second electrode, wherein the first electrode is electrically connected to the other of the source and the drain of the second transistor, and an inverted clock signal is input to the second electrode.

6. The voltage regulator circuit according to claim 4 or claim 5, wherein the off current of each of the first transistor and the second transistor is less than or equal to 10 zA/μ

m.

7. The voltage regulator circuit according to claim 4 or 5, wherein a carrier concentration of the oxide semiconductor layer of each of the first transistor and the second transistor is less than or equal to 5×

10¹⁴/cm³.

5. A voltage regulator circuit comprising n stages (n is a natural number of greater than or equal to 2) of unit step-down circuits which are electrically connected to each other in series, comprising:

a unit step-down circuit of a (2M−

1)-th stage (M is any one of 1 to n/2, and 2M is a natural number) comprising;

a first transistor including a gate, a source, and a drain, wherein an oxide semiconductor layer of the first transistor is used for a channel formation layer, and an off current of the first transistor is less than or equal to 100 zA/μ

m, and

a first capacitor including a first electrode and a second electrode, wherein the first electrode is electrically connected to the gate of the first transistor, and a clock signal is input to the second electrode; and

a unit step-down circuit of a 2M-th stage comprising;

a second transistor including a gate, a source, and a drain, wherein one of the source and the drain is electrically connected to the gate and the source or the drain of the first transistor, an oxide semiconductor layer of the second transistor is used for a channel formation layer, and an off current of the second transistor is less than or equal to 100 zA/μ

m, and

a second capacitor including a first electrode and a second electrode, wherein the first electrode is electrically connected to the gate and the other of the source and the drain of the second transistor, and an inverted clock signal is input to the second electrode.