Power stage

• US 8,963,586 B2
• Filed: 02/04/2014
• Issued: 02/24/2015
• Est. Priority Date: 07/02/2009
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Acar, Mustafa, Nowak, Katarzyna
• Primary Examiner(s): JAGER, RYAN C
• Application Number:
  US14/172,256
• Publication Number:
  US 20140152353A1
• Time in Patent Office: 385 Days
• Field of Search: 327/109, 327/112
• US Class Current: 327/110
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Claims

1. A power converter, comprising:

an input circuit configured and arranged to provide a drive signal in response to receiving an input voltage;

a level shifter configured and arranged to pass the drive signal to at least one inverter;

at least one differential buffer stage, having a high side buffer stage and a low side buffer stage, configured and arranged to receive the drive signal from the level shifter and the at least one inverter and pass the drive signal;

a high side phase shifter and a low side phase shifter each configured and arranged to shift the drive signal by 180 degrees to produce a shifted signal; and

a pair of isolation inductors configured and arranged to provide a regulated output voltage to a drive node in response to the shifted signal.

2. The power converter of claim 1, wherein the drive signal is a pulse width modulation (PWM) signal.

3. The power converter of claim 1, wherein the at least one inverter includes a first inverter and a second inverter.

4. The power converter of claim 1, wherein the at least one inverter includes a first inverter and a second inverter, and the level shifter and the first inverter are further configured and arranged between a high voltage rail and an intermediate bias voltage rail.

5. The power converter of claim 1, wherein the at least one inverter includes a first inverter and a second inverter, and the input circuit and the second inverter are further configured and arranged between a low voltage rail and an intermediate bias voltage rail.

6. The power converter of claim 1, wherein the at least one differential buffer stage includes a first buffer stage having an inverting output that drives an inverting input of a second buffer stage.