Ramp generator circuit

• US 8,963,589 B1
• Filed: 01/10/2014
• Issued: 02/24/2015
• Est. Priority Date: 01/10/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV), STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Trabattoni, Roberto, Ferrario, Lorenzo
• Primary Examiner(s): JAGER, RYAN C
• Application Number:
  US14/152,270
• Time in Patent Office: 410 Days
• Field of Search: 327131-134
• US Class Current: 327/134
• CPC Class Codes: H03K 4/50 in which a sawtooth voltage is produced across a capacitor

Abstract

An oscillator circuit selectively charges and discharges a capacitor with currents having variable magnitudes. A trimming circuit functions to measure a half period of the oscillator signal. The measured half period is compared to a reference period to generate an error signal. The variable magnitudes of one or the other or both of the current for sourcing or sinking at the capacitor are adjusted in response to the error signal.

Claims

1. A ramp generator circuit, comprising:

a capacitor;

a current source circuit configured to generate a source current having a variable magnitude;

a first switch configured to selectively apply the source current to the capacitor and generate a ramp signal at said capacitor; and

a trimming circuit configured to measure a time taken for the ramp signal to reach a threshold, compare the measured time to a reference time and adjust the variable magnitude of the source current in response to a result of the comparison.

2. The circuit of claim 1, wherein the current source circuit comprises a plurality of trim current sources each generating a trim current, and wherein said trimming circuit is configured to adjust the variable magnitude of the source current by selectively applying the trim currents from the plurality of trim current sources to the capacitor.

3. The circuit of claim 1, further comprising a switch control circuit configured to actuate the first switch at a beginning of the ramp signal and deactuate the first switch when the high threshold is reached.

4. The circuit of claim 3, wherein the trimming circuit comprises a measurement circuit configured to count a number of clock cycles between actuation and deactuation of the first switch and compare to count to the reference time to generate an error signal.

5. The circuit of claim 4, wherein the trimming circuit further comprises a trimming signal generator configured to generate a trimming signal which sets the variable magnitude of the source current in response to the error signal.

6. The circuit of claim 5, wherein the trimming signal generator is further configured to modulate the trimming signal within a modulation period having a duration less than the reference time.

7. The circuit of claim 5, wherein the trimming signal generator comprises:

a decision circuit responsive to the error signal and configured to generate a trim value and a modulation value; and

a modulation circuit configured to generate the trimming signal with a coarse adjustment value set in response to the trim value and a fine tuning adjustment value set in response to the modulation value.

8. The circuit of claim 7, wherein the decision circuit comprises:

a modulation value generator configured to adjust the modulation value in response to the error signal;

a trim value generator configured to adjust the trim value in response to a combination of the error signal and whether the modulation value has reached a threshold.

9. The circuit of claim 8, wherein the error signal indicates whether the measured time is greater than the reference time, whether the measured time equals the reference time and whether the measured time is less than the reference time.

10. The circuit of claim 9, wherein the modulation value is increased if the measured time is greater than the reference time, is not changed if the measured time equals the reference time and is decreased if the measured time is less than the reference time.

11. The circuit of claim 9, wherein the trim value is increased if the measured time is greater than the reference time and the modulation value has reached a maximum and is decreased if the measured time is less than the reference time and the modulation value has reached a minimum.

12. The circuit of claim 7, wherein the modulation circuit comprises:

a register;

a first adder circuit configured to add the modulation value to a value stored in the register and store the result in the register and further generate an overflow signal if the addition performed by the first adder circuit overflows; and

a second adder circuit configured to add the overflow signal to the trim value to generating the trimming signal.

13. An oscillator circuit, comprising:

a capacitor;

a current source circuit configured to generate a source current having a variable magnitude;

a first switch configured to selectively apply the source current to the capacitor and generate a positive ramp of an oscillator signal at said capacitor;

a current sink circuit configured to generate a sink current having a variable magnitude;

a second switch configured to selectively apply the sink current to the capacitor and generate a negative ramp of the oscillator signal at said capacitor;

a switch control circuit configured to alternately actuate the first and second switches;

a trimming circuit configured to measure a half period of the oscillator signal, compare the measured half period to a reference period and adjust the variable magnitude of the source current and sink current in response to a result of the comparison.

14. The circuit of claim 13, wherein each of the current source circuit and current sink circuit comprises a plurality of trim current sources generating trim currents which are selectively applied to the capacitor in response to the variable magnitude adjustment of the trimming circuit.

15. The circuit of claim 13, wherein the trimming circuit comprises:

a measurement circuit configured to generate an error signal in response to the comparison of the measured half period to the reference period; and

a trimming signal generator configured to generate a trimming signal which sets the variable magnitude in response to the error signal.

16. The circuit of claim 15, wherein the trimming signal generator comprises:

a decision circuit responsive to the error signal and configured to generate a trim value and a modulation value; and

a modulation circuit configured to generate the trimming signal with a coarse adjustment value set in response to the trim value and a modulated fine tuning adjustment value set in response to the modulation value.

17. The circuit of claim 16, wherein the modulation circuit comprises:

a register;

a first adder circuit configured to add the modulation value to a value stored in the register and store the result in the register and further generate an overflow signal if the addition performed by the first adder circuit overflows; and

a second adder circuit configured to add the overflow signal to the trim value to generating the trimming signal.

18. A method of generating a ramp signal, comprising:

applying a source current having a variable magnitude to a capacitor to generate a ramp signal at said capacitor;

measuring a time taken for the ramp signal to reach a threshold;

comparing the measured time to a reference time; and

adjusting the variable magnitude of the source current in response to a result of the comparison.

19. The method of claim 18, wherein comparing comprises generating an error signal indicative of a difference between the measured time taken and wherein adjusting comprises generating a trimming signal which sets the variable magnitude of the source current in response to the error signal.

20. The method of claim 19, wherein adjusting further comprises modulating the trimming signal.

21. The method of claim 19, wherein adjusting comprises:

generating a trim value and a modulation value responsive to the error signal; and

wherein said trimming signal has a coarse adjustment value set in response to the trim value and a modulated fine tuning adjustment value set in response to the modulation value.