Combinatorial circuit and method of operation of such a combinatorial circuit
First Claim
1. An integrated level shifting combinatorial circuit for receiving a plurality of input signals in a first voltage domain and performing a combinatorial operation to generate an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said integrated level shifting combinatorial circuit comprising:
- combinatorial circuitry configured to receive said plurality of input signals and to perform the combinatorial operation, the combinatorial circuitry comprising a first combinatorial circuit portion operating in said first voltage domain and a second combinatorial circuit portion operating in said second voltage domain, the second combinatorial circuit portion having an output node whose voltage level identifies a value of the output signal;
said second combinatorial circuit portion including feedback circuitry configured to apply a level shifting function to an intermediate signal generated by said first combinatorial circuit portion; and
contention mitigation circuitry operating in said second voltage domain and configured, when the combinatorial circuitry'"'"'s performance of the combinatorial operation based on the received input signals causes the combinatorial circuitry to transition the voltage on said output node between said second voltage level and said common voltage level, to reduce a voltage drop across at least one component within the feedback circuitry, thereby assisting said combinatorial circuitry in transitioning the voltage on said output node, wherein said contention mitigation circuitry includes part of said second combinatorial circuit portion, wherein said part of said second combinatorial circuit portion included within said contention mitigation circuit comprises a plurality of PMOS transistor circuits arranged in parallel, each PMOS transistor circuit receiving an associated one of said input signals from the first voltage domain.
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Abstract
An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion. A contention mitigation circuitry reduces a voltage drop across at least one component within the feedback circuitry in situations when the combinatorial circuitry'"'"'s performance of the combinatorial operation causes the combinatorial circuitry to switch the voltage on the output node, the contention mitigation circuitry thereby assists the combinatorial circuitry in the output node voltage switching.
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Citations
15 Claims
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1. An integrated level shifting combinatorial circuit for receiving a plurality of input signals in a first voltage domain and performing a combinatorial operation to generate an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said integrated level shifting combinatorial circuit comprising:
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combinatorial circuitry configured to receive said plurality of input signals and to perform the combinatorial operation, the combinatorial circuitry comprising a first combinatorial circuit portion operating in said first voltage domain and a second combinatorial circuit portion operating in said second voltage domain, the second combinatorial circuit portion having an output node whose voltage level identifies a value of the output signal; said second combinatorial circuit portion including feedback circuitry configured to apply a level shifting function to an intermediate signal generated by said first combinatorial circuit portion; and contention mitigation circuitry operating in said second voltage domain and configured, when the combinatorial circuitry'"'"'s performance of the combinatorial operation based on the received input signals causes the combinatorial circuitry to transition the voltage on said output node between said second voltage level and said common voltage level, to reduce a voltage drop across at least one component within the feedback circuitry, thereby assisting said combinatorial circuitry in transitioning the voltage on said output node, wherein said contention mitigation circuitry includes part of said second combinatorial circuit portion, wherein said part of said second combinatorial circuit portion included within said contention mitigation circuit comprises a plurality of PMOS transistor circuits arranged in parallel, each PMOS transistor circuit receiving an associated one of said input signals from the first voltage domain. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15)
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13. A method of operating an integrated level shifting combinatorial circuit configured to receive a plurality of input signals in a first voltage domain and to perform a combinatorial operation to generate an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said method comprising:
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employing combinatorial circuitry to receive said plurality of input signals and to perform the combinatorial operation, the combinatorial circuitry comprising a first combinatorial circuit portion operating in said first voltage domain and a second combinatorial circuit portion operating in said second voltage domain, the second combinatorial circuit portion having an output node whose voltage level identifies a value of the output signal; employing feedback circuitry within said second combinatorial circuit portion to apply a level shifting function to an intermediate signal generated by said first combinatorial circuit portion; and employing contention mitigation circuitry operating in said second voltage domain, when the combinatorial circuitry'"'"'s performance of the combinatorial operation based on the received input signals causes the combinatorial circuitry to transition the voltage on said output node between said second voltage level and said common voltage level, to reduce a voltage drop across at least one component within the feedback circuitry, thereby assisting said combinatorial circuitry in transitioning the voltage on said output node, wherein said contention mitigation circuitry includes part of said second combinatorial circuit portion, wherein said part of said second combinatorial circuit portion included within said contention mitigation circuitry comprises a plurality of PMOS transistor circuits arranged in parallel, each PMOS transistor circuit receiving an associated one of said input signals from the first voltage domain.
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14. An integrated level shifting combinatorial circuit for receiving a plurality of input signals in a first voltage domain and performing a combinatorial operation to generate an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said integrated level shifting combinatorial circuit comprising:
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combinatorial means for receiving said plurality of input signals and for performing the combinatorial operation, the combinatorial means comprising a first combinatorial circuit portion means for operating in said first voltage domain and a second combinatorial circuit portion means for operating in said second voltage domain, the second combinatorial circuit portion means having an output node whose voltage level identifies a value of the output signal; said second combinatorial circuit portion means including feedback means for applying a level shifting function to an intermediate signal generated by said first combinatorial circuit portion means; and contention mitigation means for operating in said second voltage domain and for reducing a voltage drop across at least one component within the feedback means when performance by the combinatorial means of the combinatorial operation based on the received input signals causes the combinatorial means to transition the voltage on said output node between said second voltage level and said common voltage level, thereby assisting said combinatorial means in transitioning the voltage on said output node, wherein said contention mitigation means includes part of said second combinatorial circuit portion means, wherein said part of said second combinatorial circuit portion means included within said contention mitigation means comprises a plurality of PMOS transistor circuits arranged in parallel, each PMOS transistor circuit receiving an associated one of said input signals from the first voltage domain.
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Specification