Semiconductor device and communication device

• US 8,963,637 B2
• Filed: 05/23/2013
• Issued: 02/24/2015
• Est. Priority Date: 05/24/2012
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Koba, Hideki, Watanabe, Keiki, Fukuda, Kouji
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US13/901,387
• Publication Number:
  US 20130314158A1
• Time in Patent Office: 642 Days
• Field of Search: 330/254, 330/9, 330/124.R
• US Class Current: 330/254
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 3/004 Control by varying the supply voltage

Abstract

A semiconductor device capable of achieving high speed performance in addition to correction of differential offset and a communication device provided with the semiconductor device are provided. For example, there are provided: a variable gain type differential amplifier circuit VGA1 which receives a gain setting signal ASET, which amplifies differential input signals INP and INN by a gain indicated by the gain setting signal, and which outputs differential output signals OUTP′ and OTUN′; and an offset correcting circuit unit OFCBK1 which cancels an offset voltage (VOF and VOFO) generated in the VGA1. Here, the OFCBK1 cancels an output offset voltage VOFO (which results in an input offset voltage VOF) by receiving the ASET, generating a correction voltage changed in accordance with the gain, and adding the correction voltage to the OUTP′ and OUTN′.

Claims

1. A semiconductor device comprising:

a variable gain type differential amplifier circuit which receives a gain setting signal, amplifies differential input signals by a gain indicated by the gain setting signal, and outputs differential output signals; and

a correcting circuit which cancels an offset voltage generated in the differential amplifier circuit;

the correcting circuit cancelling the offset voltage by receiving the gain setting signal, generating a correction voltage charged in accordance with the gain, and adding the correction voltage to the differential output signals,

wherein the correcting circuit includes a variable current source for correction connected to differential output nodes from which the differential output signals are outputted, and

the variable current source for correction generates a correction current corresponding to the correction voltage by changing a predetermined reference current in proportion to the gain, and

wherein the correcting circuit includes;

a variable current source for reference which sets a current value of the reference current;

a first reference transistor to which a current from the variable current source for reference is supplied;

a first transistor, a second transistor, a first positive electrode switch, a second positive electrode switch, a first negative electrode switch, and a second negative electrode switch, which are included in the variable current source for correction; and

a control circuit, and

the first transistor configures a current mirror circuit with the first reference transistor so as to generate a first current,

the second transistor configures a current mirror circuit with the first reference transistor so as to generate a second current,

the first positive electrode switch and the second positive electrode switch connect the first current and the second current to respective positive electrodes of the differential output nodes,

the first negative electrode switch and the second negative electrode switch connect the first current and the second current to respective negative electrodes of the differential output nodes, and,

in accordance with change of the gain setting signal, the control circuit changes ON/OFF states of the first positive electrode switch and the second positive electrode switch in a state that both of the first negative electrode switch and the second negative electrode switch are controlled to be turned OFF, or changes ON/OFF states of the first negative electrode switch and the second negative electrode switch in a state that both of the first positive electrode switch and the second positive electrode switch are controlled to be turned OFF.

2. The semiconductor device according to claim 1,

wherein the second transistor has a transistor size which is twice that of the first transistor.

3. A semiconductor device comprising:

a variable gain type first differential amplifier circuit to which first differential input signals and a first gain setting signal are inputted, which amplifies the first differential input signals by a first gain indicated by the first gain setting signal, and which outputs first differential output signals to differential output nodes;

a variable gain type second differential amplifier circuit to which second differential input signals having a reverse polarity from but the same level as those of the first differential input signals and a second gain setting signal are inputted, which amplifies the second differential input signals by a second gain indicated by the second gain setting signal, and which adds second differential amplification signals of a result of this amplification to the first differential output signals in the differential output nodes; and

a correcting circuit which cancels a first offset voltage generated in the first differential amplifier circuit, and besides, which cancels a second offset voltage generated in the second differential amplifier circuit, and

the correcting circuit cancelling the first offset voltage by receiving the first gain setting signal, generating a first correction voltage changed in accordance with the first gain, and adding the first correction voltage to the first differential output signals, and besides, cancelling the second offset voltage by receiving the second gain setting signal, generating a second correction voltage changed in accordance with the second gain, and adding the second correction voltage to the second differential output signals.

4. The semiconductor device according to claim 3,

wherein the first differential amplifier circuit is used with a fixed gain when the second gain is to be changed,

the second differential amplifier circuit is used with a fixed gain when the first gain is to be changed,

the correcting circuit includes:

a variable current source for correction connected to the differential output nodes;

a first reference current source which generates a first reference current; and

a second reference current source which generates a second reference current, and

the variable current source for correction changes the first reference current in proportion to the first gain when the first gain is to be changed so as to generate a first correction current corresponding to the first correction voltage, and changes the second reference current in proportion to the second gain when the second gain is to be changed so as to generate a second correction current corresponding to the second correction voltage.

5. The semiconductor device according to claim 3,

wherein the first differential amplifier circuit includes:

first differential pair transistors to which the first differential input signals are inputted and whose one ends are commonly connected;

a load circuit for amplification connected to the other ends of the first differential transistors; and

a first tail current source whose one end is connected to a common connection node of the first differential pair transistors,

the second differential amplifier circuit includes;

second differential pair transistors to which the second differential input signals are inputted, whose one ends are commonly connected, and whose other ends are connected to the load circuit for amplification; and

a second tail current source whose one end is connected to a common connection node of the second differential pair transistors,

a current of the first tail current source is changed in proportion to the first gain, and

a current of the second tail current source is changed in proportion to the second gain.

6. The semiconductor device according to claim 5,

wherein each of the first reference current source and the second reference current source is a variable current source, and

a first set current value of the first reference current source is determined by performing a search operation of the first set current value in a state that the first differential input signals are set to zero and that the first gain is set to the maximum gain, and

a second set current value of the second reference current source is determined by performing a search operation of the second set current value in a state that the second differential input signals are set to zero and that the second gain is set to the maximum gain.