Drive circuit, display, and method of driving display

• US 8,963,967 B2
• Filed: 08/06/2012
• Issued: 02/24/2015
• Est. Priority Date: 08/31/2011
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yoshinaga, Tomoro
• Primary Examiner(s): Kumar, Srilakshmi K
• Assistant Examiner(s): Adams, Carl
• Application Number:
  US13/567,669
• Publication Number:
  US 20130050304A1
• Time in Patent Office: 932 Days
• US Class Current: 345/694
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0266 Reduction of sub-frame artefacts
• CPC Class Codes: G09G 3/2033 with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/36 using liquid crystals

Abstract

A drive circuit includes: a division section that divides one frame period into a subfields, and divides each of one or more of the subfields to generate division subfields; a correction section that corrects, when bit arrays of the gray-scale data corresponding to respective two pixels next to each other are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two pixels to bring this bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two pixels, while maintaining gray-scale; and an ON-OFF-period control section that controls a ratio of an ON period or an OFF period to the one frame period, by turning on or off a liquid crystal cell of each of pixels according to the bit corresponding to each of the subfields and each of the division subfields.

Claims

1. A drive circuit driving each of pixels that are arranged in matrix in a display, each of the pixels being provided with a built-in memory that includes a liquid crystal cell, the drive circuit comprising:

a division section configured to divide one frame period into a plurality of subfields, and to respectively divide one or more of the plurality of subfields to generate a plurality of division subfields, respective ones of the plurality of subfields corresponding to a respective bit of gray-scale data and having a period corresponding to a weight of the corresponding bit, and respective ones of the one or more of the plurality of subfields which have a period that is relatively long are divided into periods each equal to the period of a subfield which has a period that is relatively short;

a correction section configured to rearrange, when bit arrays of the gray-scale data respectively corresponding to two adjacent pixels that are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two adjacent pixels to bring the first pixel bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two adjacent pixels, while maintaining the respective gray-scale levels of the first and second pixels; and

an ON-OFF-period control section configured to control a ratio of an ON period or an OFF period to the one frame period, by turning on or off the liquid crystal cell of each of the pixels according to the bit corresponding to each of the subfields and each of the division subfields.

2. The drive circuit according to claim 1, wherein, when the bit arrays of the two adjacent pixels are still different even after the bit array of the gray-scale data corresponding to the first pixel is brought closer to the bit array of the gray-scale data corresponding to the second pixel while the respective gray-scale levels are maintained, the correction section is further configured to increase the gray-scale level of the pixel of the two adjacent pixels that has the higher gray-scale.

3. The drive circuit according to claim 1, wherein the correction section is further configured to add a correction value common to all the pixels to the gray-scale data corresponding to each of all the pixels and periodically to change the correction value for every frame.

4. The drive circuit according to claim 1, wherein a gray-scale level of the first pixel is higher than a gray-scale level of the second pixel.

5. The drive circuit according to claim 1, wherein a gray-scale level of the second pixel is higher than a gray-scale level of the first pixel.

6. A display with a display region and a drive circuit, the display region being provided with pixels that are arranged in matrix and each having a built-in memory that includes a liquid crystal cell, and the drive circuit driving each of the pixels, the drive circuit comprising:

a division section configured to divide one frame period into a plurality of subfields, and to respectively divide one or more of the plurality of subfields to generate a plurality of division subfields, respective ones of the plurality of subfields corresponding to a respective bit of gray-scale data and having a period corresponding to a weight of the corresponding bit, and respective ones of the one or more of the plurality of subfields which have a period that is relatively long are divided into periods each equal to the period of a subfield which has a period that is relatively short;

a correction section configured to rearrange, when bit arrays of the gray-scale data respectively corresponding to two adjacent pixels that are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two adjacent pixels to bring the first pixel bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two adjacent pixels, while maintaining the respective gray-scale levels of the first and second pixels; and

an ON-OFF-period control section configured to control a ratio of an ON period or an OFF period to the one frame period, by turning on or off the liquid crystal cell of each of the pixels according to the bit corresponding to each of the subfields and each of the division subfields.

7. The display according to claim 6, wherein, when the bit arrays of the two adjacent pixels are still different even after the bit array of the gray-scale data corresponding to the first pixel is brought closer to the bit array of the gray-scale data corresponding to the second pixel while the respective gray-scale levels are maintained, the correction section is further configured to increase the gray-scale level of the pixel of the two adjacent pixels that has the higher gray-scale.

8. The display according to claim 6, wherein the correction section is further configured to add a correction value common to all the pixels to the gray-scale data corresponding to each of all the pixels and periodically to change the correction value for every frame.

9. A method of driving a display, the display being provided with pixels that are arranged in matrix and each having a built-in memory that includes a liquid crystal cell, the method comprising:

dividing one frame period into a plurality of subfields, and respectively dividing one or more of the plurality of subfields to generate a plurality of division subfields, respective ones of the plurality of subfields corresponding to a respective bit of gray-scale data and having a period corresponding to a weight of the corresponding bit, and respective ones of the one or more of the plurality of subfields which have a period that is relatively long are divided into periods each equal to the period of a subfield which has a period that is relatively short;

rearranging, when bit arrays of the gray-scale data respectively corresponding to two adjacent pixels that are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two adjacent pixels to bring the first pixel bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two adjacent pixels, while maintaining the respective gray-scale levels of the first and second pixels; and

controlling a ratio of an ON period or an OFF period to the one frame period, by turning on or off the liquid crystal cell of each of the pixels according to the bit corresponding to each of the subfields and each of the division subfields.

10. The method according to claim 9, wherein a gray-scale level of the first pixel is higher than a gray-scale level of the second pixel.

11. The method according to claim 9, wherein a gray-scale level of the second pixel is higher than a gray-scale level of the first pixel.

12. The method according to claim 9, further comprising:

increasing the gray-scale level of the pixel of the two adjacent pixels that has the higher gray-scale when the bit arrays of the two adjacent pixels are still different even after the bit array of the gray-scale data corresponding to the first pixel is brought closer to the bit array of the gray-scale data corresponding to the second pixel while the respective gray-scale levels are maintained.

13. The method according to claim 9, further comprising:

adding a correction value common to all the pixels to the gray-scale data corresponding to each of all the pixels and periodically to change the correction value for every frame.

14. The method according to claim 9, wherein a gray-scale level of the first pixel is higher than a gray-scale level of the second pixel.

15. The method according to claim 9, wherein a gray-scale level of the second pixel is higher than a gray-scale level of the first pixel.