Split current mirror line sensing

• US 8,964,412 B2
• Filed: 10/31/2012
• Issued: 02/24/2015
• Est. Priority Date: 10/31/2012
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Mao, Mingming
• Primary Examiner(s): Pham, Emily P
• Application Number:
  US13/665,173
• Publication Number:
  US 20140119059A1
• Time in Patent Office: 846 Days
• Field of Search: 363/16, 363/21.04, 363/21.12
• US Class Current: 363/16
• CPC Class Codes: H02M 1/0022 the disturbance parameters being input voltage fluctuations
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence

Abstract

Apparatus and methods for filtering the transients of an input signal of an integrated circuit while maintaining a constant voltage at an input terminal of the integrated circuit are disclosed. In one example, the integrated circuit can be a controller of a switched-mode power supply. The controller can include a line sensing circuit coupled to receive an input signal representative of the line voltage and operable produce an output signal that can be used by other circuits within the controller. The input signal may include a current through a sense resistor coupled between the input of the power supply and the line sensing circuit. The output signal may include a scaled and filtered version of this current. The line sensing circuit can be coupled to the input terminal of the controller to receive the input signal or can directly receive the input signal.

Claims

1. A controller for regulating a power converter, the controller comprising:

a line sensing circuit coupled to receive an input sense signal representative of an input voltage to the power converter, the line sensing circuit comprising;

a first transistor coupled to receive a first portion of the input sense signal; and

a current mirror coupled to receive a second portion of the input sense signal and output a filtered input sense signal; and

a control circuit coupled to receive the filtered input sense signal.

2. The controller of claim 1, wherein the current mirror comprises:

a second transistor; and

a third transistor coupled to the second transistor as a current mirror, wherein the third transistor is further coupled to output the filtered input sense signal.

3. The controller of claim 2, wherein a second terminal of the first transistor is coupled to a first terminal of the first transistor.

4. The controller of claim 3, wherein the second terminal and the first terminal of the first transistor are coupled to a first terminal of the second transistor.

5. The controller of claim 4, wherein a second terminal of the second transistor is coupled to a second terminal of the third transistor.

6. The controller of claim 5, wherein the current mirror further comprises a resistor coupled between the first terminal of the second transistor and the second terminal of the second transistor and the second terminal of the third transistor.

7. The controller of claim 6, wherein the current mirror further comprises a capacitor coupled to the second terminal of the second transistor and the second terminal of the third transistor, and wherein:

the second terminal of the first transistor comprises a gate of the first transistor;

the first terminal of the first transistor comprises a drain of the first transistor;

the first terminal of the second transistor comprises a drain of the second transistor;

the second terminal of the second transistor comprises a gate of the second transistor; and

the second terminal of the third transistor comprises a gate of the third transistor.

8. The controller of claim 2, wherein an aspect ratio of the first transistor is equal to an aspect ratio of the second transistor, and wherein an aspect ratio of the third transistor is less than the aspect ratio of the second transistor.

9. The controller of claim 1, wherein the control circuit is further coupled to:

receive a feedback signal;

receive a current sense signal; and

generate a drive signal configured to switch a power switch between an ON state and an OFF state to regulate the output of the power converter based at least in part on the filtered input sense signal, the feedback signal, and the current sense signal.

10. The controller of claim 1, wherein the line sensing circuit is operable to reduce a transient portion of the input sense signal by at least 50%.

11. The controller of claim 1, wherein the line sensing circuit is operable to maintain a voltage of the input sense signal at a substantially constant value.

12. A power converter, comprising:

a power switch; and

a controller for regulating the power converter, the controller comprising;

a line sensing circuit coupled to receive an input sense signal representative of an input voltage to the power converter, the line sensing circuit comprising;

a first transistor coupled to receive a first portion of the input sense signal; and

a current mirror coupled to receive a second portion of the input sense signal and output a filtered input sense signal; and

a control circuit coupled to receive the filtered input sense signal, wherein the control circuit is configured to generate a drive signal configured to switch the power switch between an ON state and an OFF state to regulate the output of the power converter based at least in part on the filtered input sense signal.

13. The power converter of claim 12, wherein the current mirror comprises:

a second transistor; and

a third transistor coupled to the second transistor as a current mirror, wherein the third transistor is further coupled to output the filtered input sense signal.

14. The power converter of claim 13, wherein a second terminal of the first transistor is coupled to a first terminal of the first transistor.

15. The power converter of claim 14, wherein the second terminal and the first terminal of the first transistor are coupled to a first terminal of the second transistor.

16. The power converter of claim 15, wherein a second terminal of the second transistor is coupled to a second terminal of the third transistor.

17. The power converter of claim 16, wherein the current mirror further comprises a resistor coupled between the first terminal of the second transistor and the second terminal of the second transistor and the second terminal of the third transistor.

18. The power converter of claim 17, wherein the current mirror further comprises a capacitor coupled to the second terminal of the second transistor and the second terminal of the third transistor, and wherein:

the second terminal of the first transistor comprises a gate of the first transistor;

the first terminal of the first transistor comprises a drain of the first transistor;

the first terminal of the second transistor comprises a drain of the second transistor;

the second terminal of the second transistor comprises a gate of the second transistor; and

the second terminal of the third transistor comprises a gate of the third transistor.

19. The power converter of claim 13, wherein an aspect ratio of the first transistor is equal to an aspect ratio of the second transistor, and wherein an aspect ratio of the third transistor is less than the aspect ratio of the second transistor.

20. The power converter of claim 12, wherein the line sensing circuit is operable to reduce a transient portion of the input sense signal by at least 50%.

21. The power converter of claim 12, wherein the power converter is a flyback power converter.

22. The power converter of claim 12, wherein the line sensing circuit is operable to maintain a voltage of the input sense signal at a substantially constant value.

23. A method for filtering a sense signal in a power converter, the method comprising:

receiving an input sense signal representative of an input voltage to the power converter; and

filtering, by a line sensing circuit, a transient portion of the input sense signal to generate a filtered input sense signal, wherein the line sensing circuit comprises;

a first transistor coupled to receive a first portion of the input sense signal; and

a current mirror coupled to receive a second portion of the input sense signal and output the filtered input sense signal.

24. The method of claim 23, wherein the current mirror comprises:

a second transistor; and

a third transistor coupled to the second transistor as a current mirror, wherein the third transistor is further coupled to output the filtered input sense signal.

25. The method of claim 24, wherein a second terminal of the first transistor is coupled to a first terminal of the first transistor.

26. The method of claim 25, wherein the second terminal and the first terminal of the first transistor are coupled to a first terminal of the second transistor.

27. The method of claim 26, wherein a second terminal of the second transistor is coupled to a second terminal of the third transistor.

28. The method of claim 27, wherein the current mirror further comprises a resistor coupled between the first terminal of the second transistor and the second terminal of the second transistor and the second terminal of the third transistor.

29. The method of claim 28, wherein the current mirror further comprises a capacitor coupled to the second terminal of the second transistor and the second terminal of the third transistor, and wherein:

the second terminal of the first transistor comprises a gate of the first transistor;

the first terminal of the first transistor comprises a drain of the first transistor;

the first terminal of the second transistor comprises a drain of the second transistor;

the second terminal of the second transistor comprises a gate of the second transistor; and

the second terminal of the third transistor comprises a gate of the third transistor.

30. The method of claim 24, wherein an aspect ratio of the first transistor is equal to an aspect ratio of the second transistor, and wherein an aspect ratio of the third transistor is less than the aspect ratio of the second transistor.

31. The method of claim 23, wherein filtering the transient portion of the input sense signal to generate the filtered input sense signal comprises reducing the transient portion of the input sense signal by at least 50%.

32. The method of claim 23, wherein filtering the transient portion of the input sense signal to generate the filtered input sense signal comprises maintaining a voltage of the input sense signal at a substantially constant value.

33. A power converter, comprising:

a power switch;

a controller for regulating the power converter, the controller comprising;

a line sensing circuit coupled to receive an input sense signal representative of an input voltage to the power converter, the line sensing circuit comprising;

a first transistor coupled to receive a first portion of the input sense signal; and

a current mirror coupled to receive a second portion of the input sense signal and output a filtered input sense signal; and

a control circuit coupled to receive the filtered input sense signal, wherein the control circuit is configured to generate a drive signal configured to switch the power switch between an ON state and an OFF state to regulate the output of the power converter based at least in part on the filtered input sense signal; and

a sense resistor coupled between an input of the power converter and the first transistor, wherein an impedance of the sense resistor is between 1-10 MOhms, and wherein a drain-to-source impedance of the first transistor is between 200-5000 Ohms.