Write driver circuit with low voltage bootstrapping for write assist

• US 8,964,490 B2
• Filed: 02/07/2013
• Issued: 02/24/2015
• Est. Priority Date: 02/07/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Chow, Daniel C, Huang, Hang, Bhatia, Ajay Kumar, Sullivan, Steven C
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US13/761,646
• Publication Number:
  US 20140219009A1
• Time in Patent Office: 747 Days
• Field of Search: 365/189.16, 365/189.11, 365/189.06, 365/189.02, 365/230.03, 365/156, 365/154, 365/190, 365/228, 365/226
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may be configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

Claims

1. An apparatus, comprising:

a write driver circuit configured to;

initialize an output node to a first voltage level; and

discharge the output node to a second voltage level responsive to a write data signal;

wherein the second voltage level is lower than the first voltage level; and

a boost circuit coupled to the output node, wherein the boost circuit is configured to couple the output node to a third voltage level responsive to a boost control signal, wherein the third voltage level is lower than the second voltage level.

2. The apparatus of claim 1, wherein the boost circuit includes a capacitor, and wherein the capacitor is coupled to the output node and a boost node.

3. The apparatus of claim 2, wherein the boost circuit is further configured to initialize the boost node to the first voltage level.

4. The apparatus of claim 3, wherein to couple the output node to a third voltage level, the boost circuit is further configured to discharge the boost node to the second voltage level.

5. The apparatus of claim 1, wherein the first voltage level is a power supply potential.

6. A method, comprising:

initializing an output node of a write driver circuit included in a memory circuit to a first voltage level, wherein the output node is coupled to a data line, and wherein the data line is coupled to a plurality of data storage cells;

discharging the output node to a second voltage level, wherein the second voltage level is lower than the first voltage level; and

coupling the output node to a third voltage level, wherein the third voltage level is lower than the second voltage level;

wherein coupling the output node to the third voltage level comprises discharging a selected one of a plurality of boost nodes dependent upon an activation of a respective one of a plurality of selection signals.

7. The method of claim 6, wherein the discharging the output node is responsive to a write data signal.

8. The method of claim 6, wherein coupling the output node to a third voltage level is responsive to a boost control signal.

9. The method of claim 6, wherein coupling the output node to a third voltage level comprises, initializing, to the first voltage level, a boost node coupled to a capacitor, wherein the capacitor is further coupled to the output node.

10. The method of claim 9, wherein the coupling the output node to a third voltage level further comprises, discharging the boost node to the second voltage level.

11. The method of claim 6, wherein discharging the output node comprises:

initializing a common node to the second voltage level; and

discharging the output node into the common node.

12. The method of claim 11, wherein the common node is coupled to a second output node.

13. A memory, comprising:

a data input circuit configured to latch input data to the memory;

an address decode circuit configured to;

decode an input address to the memory;

activate one of a plurality of column selection signals responsive to the decoded input address;

a plurality of sub-arrays, wherein each sub-array includes;

a plurality of columns, wherein each column of the plurality of columns includes a plurality of data storage cells;

a write selection circuit coupled to the plurality of columns, wherein the write selection circuit is configured to select one of the plurality of columns responsive to the activation of a respective one of the plurality of column selection signals;

a first write driver circuit coupled to a data input of the write selection circuit, wherein the first write driver circuit is configured to discharge the data input of the write selection circuit into a common node dependent upon the latched input data;

a second write driver circuit coupled to a complement data input of the write selection circuit, wherein the second write driver circuit is configured to discharge the complement data input of the write selection circuit into the common node dependent upon the latched input data; and

a boost circuit coupled to the common node, wherein the boost circuit is configured to;

initialize the common node to a first voltage level; and

couple the common node to a second voltage level, wherein the second voltage level is lower than the first voltage level.

14. The memory of claim 13, wherein the boost circuit comprises a plurality of capacitors, wherein each capacitor of the plurality of capacitors is coupled between the common node and a respective one of a plurality of boost nodes.

15. The memory of claim 14, wherein each capacitor of the plurality of capacitors comprises a metal-oxide semiconductor field-effect transistor (MOSFET).

16. The memory of claim 14, wherein the boost circuit is further configured to initialize each of the plurality of boost nodes to a third voltage level.

17. The memory of claim 16, wherein the boost circuit is further configured to discharge a selected one of the plurality of boost nodes dependent upon the activation of a respective one of a plurality of selection signals.

18. The memory of claim 13, wherein each of the plurality of data storage cells comprises a static random access memory (SRAM) cell.