Apparatuses and methods for performing compare operations using sensing circuitry

• US 8,964,496 B2
• Filed: 07/26/2013
• Issued: 02/24/2015
• Est. Priority Date: 07/26/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/952,054
• Publication Number:
  US 20150029798A1
• Time in Patent Office: 578 Days
• Field of Search: 365/189.07, 365/201
• US Class Current: 365/201
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Claims

1. A method of performing a compare function, comprising:

charging an input/output (IO) line of a memory array to a voltage;

determining whether data stored in the memory array matches a compare value by;

activating a number of access lines of the memory array;

sensing a number of memory cells coupled to the number of access lines; and

sensing, via a secondary sense amplifier, whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

2. The method of claim 1, wherein charging an IO line includes precharging an IO line of the memory array to a precharge voltage.

3. The method of claim 1, wherein charging the IO line to the voltage includes charging the IO line to a supply voltage.

4. The method of claim 3, wherein the supply voltage corresponds to a data value of 1.

5. The method of claim 1, wherein charging the IO line to a voltage includes charging the IO line to a ground voltage.

6. The method of claim 5, wherein the ground voltage corresponds to a data value of 0.

7. The method of claim 1, wherein activating selected decode lines comprises activating a subset of the decode lines of the array.

8. The method of claim 7, including determining the subset of decode lines based on a set of criteria of the subset.

9. An apparatus comprising:

an array of memory cells;

control circuitry coupled to the array and configured to cause;

precharging of a local input/output (LIO) line of the array to a precharge voltage; and

selective activation of access lines and decode lines of the array; and

sensing circuitry coupled to the array and configured to;

sense a number of selected memory cells coupled to an activated access line; and

determine, using a secondary sense amplifier, whether the precharge voltage of the LIO line changes in response to activation of decode lines corresponding to the number of selected memory cells.

10. The apparatus of claim 9, wherein the control circuitry comprises an on die controller.

11. The apparatus of claim 9, wherein the control circuitry comprises an external host.

12. The apparatus of claim 9, wherein the precharge voltage corresponds to a particular data value and a determined change in the precharge voltage of the LIO line indicates that a selected memory cell corresponding to an activated decode line stores a data value other than the particular data value.

13. The apparatus of claim 9, wherein the sensing circuitry comprises the secondary sense amp configured to detect whether the precharge voltage of the LIO line changes.

14. The apparatus of claim 9, wherein a determined change in the precharge voltage of the LIO line indicates data in a memory cell matches a compare value.

15. The apparatus of claim 9, wherein the control circuitry is configured to report a determined change in the precharge voltage of the LIO line to a host.

16. The apparatus of claim 9, wherein the sensing circuitry is configured to provide an indication that a determined change in the precharge voltage of the LIO line was detected.

17. An apparatus comprising:

an array of memory cells;

control circuitry coupled to the memory array and configured to cause a charging of an input/output (IO) line of the memory array to a voltage; and

sensing circuitry coupled to the memory array and comprising;

a number of primary sense amplifiers coupled to respective pairs of complementary sense lines;

a number of accumulators coupled to the number of primary sense amplifiers;

a secondary sense amplifier coupled to the IO line and configured to sense whether the voltage of the IO line changes in response to activation of selected decode lines of the array to determine whether data stored in the array matches a compare value.

18. The apparatus of claim 17, wherein each of the accumulators comprises:

a first pass transistor having a first source/drain region coupled to a first sense line of a pair of complementary sense lines;

a second pass transistor having a first source/drain region coupled to a second sense line of the pair of complementary sense lines; and

a first pair of cross coupled transistors and a second pair of cross coupled transistors.

19. The apparatus of claim 18, wherein the apparatus is configured to perform a logical operation that comprises performing an accumulate operation on a data value represented by a signal on at least one of the pair of complementary sense lines.

20. The apparatus of claim 19, wherein the signal is provided to the IO line through at least one of the number of primary sense amplifiers.

21. The apparatus of claim 20, wherein charging an IO line to a voltage includes precharging an IO line of the memory array to a precharge voltage.

22. The apparatus of claim 21, wherein the signal is provided to the secondary sense amplifier, and wherein the secondary sense amplifier detects a change in the precharge voltage when the signal corresponds to a voltage that is different than the precharge voltage.

23. The apparatus of claim 19, wherein the accumulator is configured to receive an invert signal, wherein activating the invert signal inverts a data value stored in the accumulator and drives a signal corresponding to the inverted data value onto one of the pair of complementary sense lines.

24. The apparatus of claim 23, wherein the pair of complementary sense lines is configured to provide the signal corresponding to the inverted data value to at least one of the number of primary sense amplifiers.

25. The apparatus of claim 24, wherein the at least one of the number of primary sense amplifiers is configured to provide the inverted data value to the IO_line, wherein the IO_line is configured to provide the inverted data value to the secondary sense amplifier.

26. The apparatus of claim 25, wherein the IO_line is charged to a ground voltage and wherein the secondary sense amplifier detects a change in the voltage when the signal corresponding to the inverted data value is a greater voltage than a ground voltage.

27. An apparatus comprising:

an array of memory cells;

control circuitry coupled to the array and configured to, as part of a compare operation;

cause precharging of a local input/output (LIO) line of the array to a precharge voltage;

cause selective activation of access lines of the array; and

cause selective activation of decode lines of the array; and

sensing circuitry coupled to the array and configured to;

sense memory cells coupled to a plurality of selectively activated access lines; and

sense, using a secondary sense amplifier, whether the precharge voltage of the LIO line changes in response to selective activation of a plurality of the decode lines corresponding to the memory cells;

wherein a determination that the precharge voltage changes in response to the selective activation of the plurality of column decode lines indicates that at least one of the memory cells coupled to the plurality of selectively activated access lines stores a data value that matches a compare value.

28. The apparatus of claim 27, comprising control circuitry configured to cause the determination that the at least one of the memory cells stores a data value that matches the compare value to be reported back into the array.

29. The apparatus of claim 27, comprising control circuitry configured to cause a search to identify which memory cell of the at least one of the memory cells matched the compared value.

30. The apparatus of claim 29, comprising control circuitry configured to cause the identification of the memory cell to be reported to a host.

31. The apparatus of claim 29, comprising control circuitry configured to cause the identification of the memory cell to be reported back into the array.