Method and system for low power transmission and data alignment

• US 8,964,791 B2
• Filed: 10/11/2012
• Issued: 02/24/2015
• Est. Priority Date: 10/11/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Vu, Mieu Van, Vaglica, John J.
• Primary Examiner(s): Yao, Kwang B
• Assistant Examiner(s): LOO, JUVENA W
• Application Number:
  US13/649,461
• Publication Number:
  US 20140105101A1
• Time in Patent Office: 866 Days
• Field of Search: 370445-520
• US Class Current: 370/504
• CPC Class Codes: H04L 1/0008 by supplementing frame payload, e.g. with padding bits
• CPC Class Codes: H04W 24/06 Testing, supervising or monitoring using simulated traffic
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A method and apparatus automatically maintains a JESD204 serial data link (252) as active by using an idle signal (254) and multiplexer selection circuit (247) to selectively switch signal data samples (246) and dummy samples (0, . . . 0) onto a serial interface input to a JESD module (248) for serialization into a plurality of symbols for transmission over the JESD204 serial data link (252) in response to a transmit clock signal (253) so that serialized symbols generated from signal data samples are transmitted when there are signal data samples available, and serialized symbols generated from dummy samples are transmitted when there are no signal data samples available.

Claims

1. A method for operating a first base station subsystem, comprising:

generating signal data samples for transmission over a first high speed serial data link;

generating dummy samples for transmission over the first high speed serial data link;

switching the signal data samples and the dummy samples onto a serial interface input in response to an idle condition having first and second values such that any available signal data samples are switched onto the serial interface input when the idle condition is of a first state, and the dummy samples are switched onto the serial interface input when the idle condition is of a second state;

serializing the signal data and dummy samples from the serial interface input into a plurality of symbols for transmission over the first high speed serial data link;

providing a plurality of RF control signals to a transceiver subsystem which is connected to receive the plurality of symbols over the first high speed serial data link to simultaneously disable RF signal reception and enable RF signal transmission at the transceiver subsystem when a transmission enable control signal is in a first phase, and to simultaneously enable RF signal reception and disable RF signal transmission at the transceiver subsystem when the transmission enable control signal is in a second phase; and

transmitting the plurality of symbols over the first high speed serial data link, wherein the first high speed serial data link is maintained as active by transmitting the plurality of symbols generated from the dummy samples when there are no signal data samples available.

2. The method of claim 1, further comprising generating an idle clock signal having the first and second values in response to the idle condition having first and second values.

3. The method of claim 1, where the first high speed serial data link is a Joint Electron Devices Engineering Council (JEDEC) Standards Document JESD204-compliant serial interface link.

4. The method of claim 1, where switching the signal data samples and the dummy samples onto the serial interface input comprises applying an idle clock signal as a selection control input to a multiplexer selection circuit which has a first input connected to receive the signal data samples and a second input connected to receive the dummy samples.

5. The method of claim 1, where generating the dummy samples comprises applying a string of zero values for transmission over the first high speed serial data link when the idle condition is of the second state.

6. The method of claim 1, where serializing samples from the serial interface input comprises:

framing bits of the signal data samples and the dummy samples from the serial interface input into N-bit data words;

mapping each N-bit data word to an M-bit symbol; and

serializing each M-bit symbol for transfer over the first high speed serial data link.

7. The method of claim 1, where serializing the signal data samples and the dummy samples from the serial interface input comprises generating a transmit clock signal with a local clock generator and frame synchronizer such that the transmit clock signal is synchronous to a network radio frame.

8. The method of claim 7, where transmitting the plurality of symbols over the first high speed serial data link comprises transmitting the serialized symbols generated from the signal data samples in alignment with the network radio frame.

9. The method of claim 1, further comprising enabling a control processor at the first base station subsystem to enter a low power mode while maintaining the first high speed serial data link as active by transmitting the plurality of symbols generated from the dummy samples when there are no signal data samples available.

10. A method for operating a first base station subsystem connected to a transceiver subsystem over a first high speed transmit serial data link and a second high speed receive serial data link used in a time division duplex mode, comprising:

switching signal data samples and dummy samples into a high speed transmit serial interface for serializing the signal data samples and dummy samples into a plurality of symbols in response to an idle signal having first and second phases, such that the signal data samples are switched into the high speed transmit serial interface when the idle signal is in the first phase, and the dummy samples are switched into the high speed transmit serial interface when the idle signal is in the second phase;

transmitting the plurality of symbols from the high speed transmit serial interface over the first high speed transmit serial data link to the transceiver subsystem so that the first high speed transmit serial data link is maintained as active by transmitting the plurality of symbols generated from the dummy samples when there are no signal data samples available; and

providing a plurality of RF control signals to the transceiver subsystem to simultaneously disable RF signal reception and enable RF signal transmission when a transmission enable control signal is in a first phase, and to simultaneously enable RF signal reception and disable RF signal transmission when the transmission enable control signal is in a second phase.

11. The method of claim 10, where providing the plurality of RF control signals comprises:

generating a transmission enable control signal having first and second phases for respectively enabling and disabling RF signal transmission, where the transitions from the second phase to the first phase in the transmission enable control signal precede transitions from the second phase to the first phase in the idle signal by a specified transmitter transient period; and

generating a receive enable control signal having first and second phases for respectively disabling and enabling RF signal reception, where the transitions from the second phase to the first phase in the receive enable control signal precede transitions from the second phase to the first phase in the idle signal by the specified transmitter transient period.

12. The method of claim 11, where providing the plurality of RF control signals comprises:

generating the transmission enable control signal to have transitions from the first phase to the second phase which are delayed by a specified transmitter transient period with respect to transitions from the first phase to the second phase in the idle signal; and

generating the receive enable control signal to have transitions from the first phase to the second phase which are delayed by a specified transmitter transient period with respect to transitions from the first phase to the second phase in the idle signal.

13. The method of claim 10, where providing the plurality of RF control signals comprises:

generating a power amplifier control signal having first and second phases for respectively turning on and off a power amplifier in the transceiver subsystem, where the transitions from the second phase to the first phase in the power amplifier control signal precede transitions from the second phase to the first phase in the idle signal by a specified transmitter transient period; and

generating a low noise amplifier control signal having first and second phases for respectively turning off and on a low noise amplifier in the transceiver subsystem, where the transitions from the second phase to the first phase in the low noise amplifier control signal precede transitions from the second phase to the first phase in the power amplifier control signal by the specified transient period.

14. The method of claim 13, where providing the plurality of RF control signals comprises:

generating the power amplifier control signal to have transitions from the first phase to the second phase which are delayed by a specified transient period with respect to transitions from the first phase to the second phase in the idle signal; and

generating the low noise amplifier control signal to have transitions from the first phase to the second phase which are delayed by a specified transmitter transient period with respect to transitions from the first phase to the second phase in the idle signal.

15. The method of claim 10, where transmitting the plurality of symbols comprises transmitting the plurality of symbols over a Joint Electron Devices Engineering Council (JEDEC) Standards Document JESD204-compliant serial interface link.

16. The method of claim 10, where switching signal data samples comprises:

applying the idle signal as a selection control input to a multiplexer selection circuit which has a first input connected to receive the signal data samples, a second input connected to receive the dummy samples, and an output; and

serializing samples from the multiplexer selection circuit output in response to a transmit clock signal that is generated with a local clock generator and frame synchronizer such that the transmit clock signal is synchronous to a network radio frame.

17. The method of claim 10, further comprising enabling a control processor at the first base station subsystem to synchronize processing functionality at the first base station subsystem with the transceiver subsystem in the time division duplex mode, and to determine whether the first base station subsystem can enter a low power mode or exit from the low power mode.

18. An integrated circuit for a local base station subsystem connected to at least a first base station subsystem, the integrated circuit comprising:

a first clock generator for generating a transmit clock signal that is synchronous to a network radio frame;

a second clock generator for generating an idle signal having first and second values;

a transmit interface for transmitting symbols over a serial interface link to the first base station subsystem comprising;

a serial interface for serializing samples switched into the serial interface into a plurality of symbols for transmission over the serial interface link in response to the transmit clock signal; and

a switching circuit for switching signal data samples and dummy samples into the serial interface in response to the idle signal, such that the signal data samples are switched into the serial interface when the idle signal has the first value, and the dummy samples are switched into the serial interface when the idle signal has the second value; and

a transceiver subsystem connected to receive the plurality of symbols over the first high speed serial data link, where the transceiver subsystem receives a plurality of RF control signals to simultaneously disable RF signal reception and enable RF signal transmission at the transceiver subsystem when a transmission enable control signal is in a first phase, and to simultaneously enable RF signal reception and disable RF signal transmission at the transceiver subsystem when the transmission enable control signal is in a second phase.

19. The integrated circuit of claim 18, where switching circuit comprises a multiplexer selection circuit which has a first data input connected to receive the signal data samples, a second data input connected to receive the dummy samples, a first control input connected to receive the idle signal as a selection control input, and an output.