Information processing system

• US 8,966,215 B2
• Filed: 02/14/2013
• Issued: 02/24/2015
• Est. Priority Date: 03/19/2012
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Noguchi, Yasuo, Ozawa, Toshihiro, Oe, Kazuichi, Maeda, Munenori, Ogihara, Kazutaka, Tamura, Masahisa, Iizawa, Ken, Kumano, Tatsuo, Kato, Jun
• Primary Examiner(s): Li, Aimee
• Assistant Examiner(s): BLUST, JASON W
• Application Number:
  US13/766,816
• Publication Number:
  US 20130246717A1
• Time in Patent Office: 740 Days
• Field of Search: None
• US Class Current: 711/170
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]

Abstract

An information processing system includes: CPUs; storage devices; switches; dummy storage devices which are with respective storage devices and each of which sends, when receiving an identifying information request, its own identifying information back to a sender of the identifying information request; and dummy CPUs which are associated with respective CPUs and each of which tries to, when receiving an instruction for acquiring identifying information from a dummy storage device, acquire the identifying information of the dummy storage device by transmitting the identifying information request, and sends the identifying information as response information back to a sender device of the acquiring instruction.

Claims

1. An information processing system comprising:

first through N-th (N≧

2) central processing units (CPUs) ;

first through N-th dummy CPUs associated respectively with the first through N-th CPUs;

first through M-th (M≧

2) storage devices;

first through M-th dummy storage devices associated respectively with the first through M-th storage devices;

a main switch including at least (N+M) number of ports;

first through N-th dedicated CPU switches associated respectively with the first through N-th CPUs, each of the first through N-th dedicated CPU switches having a port group including at least three ports; and

first through M-th dedicated storage device switches associated respectively with the first through M-th storage devices, each of the first through M-th dedicated storage device switches having a port group including at least three ports,

wherein the port group of each dedicated CPU switch among the first through N-th dedicated CPU switches is connected to a CPU among the first through N-th CPUs which is associated with the each dedicated storage switch, to a dummy CPU among the first through N-th dummy CPUs which is associated with the CPU, and to one port of the main switch,

the port group of each dedicated storage device switch among the first through M-th dedicated storage device switches is connected to a storage device among the first through M-th storage devices which is associated with the each dedicated storage device switch, to a dummy storage device among the first through M-th dummy storage devices associated with the storage device, and to one port of the main switch,

each of the first through M-th dummy devices is a device that sends, when receiving an identifying information request, its own identifying information back to a sender of the identifying information request, and

each of the first through N-th dummy CPUs is a device that tries to, when receiving an instruction of acquiring identifying information from a dummy storage device among the first through M-th storage devices, acquire the identifying information of the dummy storage device by transmitting the identifying information request, and sends the identifying information as response information back to a sender device of the acquiring instruction.

2. The information processing system according to claim 1, further comprising a connection management apparatus to control connection relations between the ports of the first through N-th dedicated CPU switches and the first through M-th dedicated storage device switches,

wherein the connection management apparatus, when instructed to establish the connection between a J-th (N≧

J≧

1) CPU and a K-th (M≧

K≧

1) storage device, transmits an instruction of acquiring identifying information from the K-th dummy storage device to the J-th dummy CPU after controlling one or more switches among the main switch, the J-th dedicated CPU switch and the K-th dedicated storage device so that the J-th dummy CPU is connected to the K-th dummy storage device, and controls the J-th dedicated CPU switch and/or the K-th dedicated storage device so that the J-th CPU is connected to the K-th storage device if the response information given from the J-th dummy CPU in response to the acquiring instruction is the identifying information of the K-th dummy storage device.

3. The information processing system according to claim 1, wherein each of the first through N-th dummy CPUs, when receiving the instruction of acquiring the identifying information from a certain dummy storage device, tries to the identifying information of the dummy storage device by transmitting the identifying information request, and sends, if the identifying information is acquired, the identifying information as response information back to the sender device of the acquiring instruction but sends, whereas if the identifying information is not be acquired, information indicating this purport as response information back to the sender device.

4. The information processing system according to claim 2, wherein the connection management apparatus, if the response information given from the J-th dummy CPU in response to the acquiring instruction is not the identifying information of the K-th dummy storage device, displays a message indicating this purport on a display.

5. An information processing system comprising:

first through N-th (N≧

2) CPUs;

first through N-th dummy CPUs associated respectively with the first through N-th CPUs;

first through M-th (M≧

2) storage devices;

a main switch including at least (N+M) number of ports; and

first through N-th dedicated CPU switches associated respectively with the first through N-th CPUs, each of the first through N-th dedicated CPU switches having a port group including at least three ports,

wherein the port group of each dedicated CPU switch among the first through N-th dedicated CPU switches is connected to a CPU among the first through N-th CPUs which is associated with the each dedicated storage switch, to a dummy CPU among the first through N-th dummy CPUs which is associated with the CPU, and to one port of the main switch,

the first through M-th storage devices are connected to ports, different from each other, of the main switch, to which the dedicated CPU switches are not connected, and

each of the first through N-th dummy CPUs is a device that, when receiving an instruction acquiring identifying information from a certain storage device among first through M-th storage devices, tries to acquire the identifying information of the storage device, and sends the identifying information as response information back to a sender device of the acquiring instruction if the identifying information can be acquired.

6. The information processing system according to claim 5, wherein a relay unit, which relays data between the each of the first through M-th storage device and the main switch and sends, when receiving an identifying information output instruction from a dummy CPU among the first through N-th dummy CPUs, storage device identifying information set therein back to the dummy CPU, is provided between each of the first through M-th storage device and the main switch.