Optimizing power usage by factoring processor architectural events to PMU
First Claim
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1. A processor comprising:
- a plurality of cores, each core including;
a plurality of thermal sensors to provide thermal data for the core and a plurality of counters each to count a number of occurrences of an architectural event;
a bus to couple the plurality of counters and the plurality of thermal sensors; and
a power control unit coupled to the bus to modify a power state of one of the plurality of cores in response to an occurrence of an architectural event in the one of the plurality of cores.
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Abstract
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
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Citations
20 Claims
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1. A processor comprising:
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a plurality of cores, each core including; a plurality of thermal sensors to provide thermal data for the core and a plurality of counters each to count a number of occurrences of an architectural event; a bus to couple the plurality of counters and the plurality of thermal sensors; and a power control unit coupled to the bus to modify a power state of one of the plurality of cores in response to an occurrence of an architectural event in the one of the plurality of cores. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method comprising:
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generating a signal to indicate an occurrence of an architectural event at a core of a multicore processor, wherein the architectural event is to be monitored by a channel programmed with information corresponding to the architectural event; communicating the signal to a power control unit of the multicore processor via a bus shared with thermal sensor circuitry of the multicore processor; and causing a power sequence based on the occurrence of the architectural event, wherein the power control unit is to determine whether to modify a power state of the core based on a value of one or more of a plurality of counters each corresponding to an architectural event. - View Dependent Claims (15, 16)
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17. A system comprising:
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a processor including logic circuitry to detect whether an architectural event has occurred within a first core using a channel programmed with information corresponding to the architectural event, a plurality of counters each to count a number of occurrences of one of a plurality of architectural events within the first core, a bus to couple the plurality of counters, and a power control unit to cause a second core to enter into a turbo mode in response to the number of occurrences of one or more of the plurality of counters; and a dynamic random access memory (DRAM) coupled to the processor. - View Dependent Claims (18, 19, 20)
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Specification