Redundancy for loss-tolerant data in non-volatile memory

• US 8,966,310 B2
• Filed: 11/15/2012
• Issued: 02/24/2015
• Est. Priority Date: 11/15/2012
• Status: Expired due to Fees

• Current Assignee: Elwha LLC (Intellectual Ventures LLC)
• Original Assignee: Elwha LLC (Intellectual Ventures LLC)
• Inventors: Hyde, Roderick A., Pasch, Nicholas F., Tegreene, Clarence T.
• Primary Examiner(s): KO, CHAE M
• Application Number:
  US13/678,439
• Publication Number:
  US 20140136903A1
• Time in Patent Office: 831 Days
• Field of Search: 714/6.13
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G11C 29/886 combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device

Abstract

A memory device includes a memory array including a plurality of memory sections characterized by a plurality of memory types and control logic integrated with and distributed over the memory array. The control logic is operable to selectively allocate redundant sections in the plurality of memory sections.

Claims

1. A memory device comprising:

a memory array comprising a plurality of memory sections characterized by a plurality of memory types; and

control logic integrated with and distributed over the memory array, the control logic operable to selectively allocate redundant sections in the plurality of memory sections.

2. The memory device according to claim 1 wherein:

the memory array includes the plurality of memory sections including a plurality of different operating characteristics; and

the control logic is operable to allocate the redundant sections to memory sections with different operating characteristics.

3. The memory device according to claim 1 wherein:

the memory array includes the plurality of memory sections including a plurality of different failure conditions; and

the control logic is operable to allocate the redundant sections to memory sections with different failure conditions.

4. The memory device according to claim 1 wherein:

the memory array includes the plurality of memory sections including at least one memory section susceptible to failure due to a temperature condition and at least one memory section resistant to the failure due to the temperature condition; and

the control logic is operable to allocate the at least one memory section resistant to the failure due to the temperature condition redundant to the at least one memory section susceptible to failure due to a temperature condition.

5. The memory device according to claim 1 wherein:

the memory array includes the plurality of memory sections including at least one memory section susceptible to failure due to a magnetic field condition and at least one memory section resistant to the failure due to the magnetic field condition; and

the control logic is operable to allocate the at least one memory section resistant to the failure due to the magnetic field condition redundant to the at least one memory section susceptible to failure due to a magnetic field condition.

6. The memory device according to claim 1 wherein:

a memory array including at least one memory section including fast memory and at least one memory section including slow memory that has slower access speed than the at least one memory section including fast memory; and

the control logic is operable to selectively allocate portions of the memory section including fast memory and the memory section including slow memory that are mutually redundant.

7. The memory device according to claim 1 wherein:

the memory array includes a first memory section and a second memory section that is redundant to the first memory section; and

the control logic is operable to represent data in the second memory section as a hash of data in the first memory section.

8. The memory device according to claim 1 wherein:

the memory array includes a first memory section and a second memory section that is redundant to the first memory section; and

the control logic is operable to dump data in the first memory section to the second memory section at selected times.

9. The memory device according to claim 1 wherein:

the memory array includes at least one redundant non-volatile memory array; and

the control logic is operable to dump data to the at least one redundant non-volatile memory array at selected times.

10. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks characterized by a plurality of different operating characteristics; and

the control logic is operable to selectively manage redundant sections in the plurality of memory blocks based on at least one of the a plurality of different operating characteristics.

11. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks characterized by a plurality of different operating characteristics; and

the control logic is operable to analyze memory accesses and selectively manage redundant sections in the plurality of memory blocks based on the analysis.

12. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks characterized by a plurality of different operating characteristics; and

the control logic is operable to analyze memory accesses, determine application constraints based on the analysis, and selectively manage redundant sections in the plurality of memory blocks based on the determined application constraints.

13. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks characterized by a plurality of different operating characteristics; and

the control logic is operable to analyze memory accesses, determine priority of performance based on the analysis, and selectively manage redundant sections in the plurality of memory blocks based on the determined priority of performance.

14. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks; and

the control logic is operable to analyze memory accesses, perform error detection based on the analysis, characterize Quality-of-Service (QoS) ratings of the plurality of memory blocks based on the performed error detection, and selectively manage redundant sections in the plurality of memory blocks based on the characterized QoS ratings.

15. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks; and

the control logic is operable to receive a report on operating conditions of system performance at system bootstrap loading, and selectively manage redundant sections in the plurality of memory blocks based on the report.

16. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks; and

the control logic is operable to monitor writes to the plurality of memory blocks of the non-volatile memory array, and selectively manage redundant sections in the plurality of memory blocks based on results of the monitoring.

17. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks; and

the control logic is operable to monitor operating characteristics of the memory device, analyze the monitored operating characteristics, detect a precursor to a memory failure based on the analysis, and selectively manage redundant sections in the plurality of memory blocks based on the detected precursor.

18. The memory device according to claim 1 further comprising:

at least one sensor operable to detect an operating condition, wherein;

the memory array includes at least one non-volatile memory array including a plurality of memory blocks; and

the control logic is operable to monitor the operating condition, analyze the monitored operating condition, detect a precursor to a memory failure based on the analysis, and selectively manage redundant sections in the plurality of memory blocks based on the detected precursor.

19. The memory device according to claim 1 further comprising:

at least one sensor operable to detect an operating condition, wherein;

the memory array includes at least one non-volatile memory array including a plurality of memory blocks; and

the control logic is operable to monitor the operating condition, analyze the monitored operating conditions, predict expected outcomes based on the analysis of the monitored operating conditions, and selectively manage redundant sections in the plurality of memory blocks based on the predicted expected outcomes.

20. The memory device according to claim 1 further comprising:

at least one sensor operable to detect an operating condition, wherein;

the memory array includes at least one non-volatile memory array including a plurality of memory blocks; and

the control logic is operable to monitor the operating condition, monitor memory accesses, analyze the monitored operating conditions and memory accesses, predict expected outcomes based on the analysis of the monitored operating conditions and memory accesses, and selectively manage redundant sections in the plurality of memory blocks based on the predicted expected outcomes.

21. The memory device according to claim 1 further comprising:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks; and

the control logic is operable to access a time signal, monitor memory accesses referenced by the time signal, analyze workload based on the monitored memory accesses, and selectively manage redundant sections in the plurality of memory blocks based on the analyzed workload.

22. The memory device according to claim 1 further comprising:

the memory array includes at least one non-volatile memory array including a plurality of memory blocks including at least one memory block including lossy memory; and

the control logic is operable to monitor memory accesses, analyze the memory accesses to determine instructions and data indicative for storage in the at least one memory block including lossy memory, and selectively manage redundant sections in the plurality of memory blocks including lossy memory.

23. The memory device according to claim 1 wherein:

the control logic is operable to monitor a history and pattern of memory accesses and selectively manage redundant sections in the plurality of memory sections during system idle.

24. The memory device according to claim 1 wherein:

the control logic is operable to monitor memory accesses, perform pattern recognition of the monitored memory accesses, and selectively manage redundant sections in the plurality of memory sections based on recognized patterns.

25. The memory device according to claim 1 wherein:

the control logic is operable to manage redundant sections in the plurality of memory sections independently of signals external to the memory device.

26. The memory device according to claim 1 wherein:

the control logic is operable to monitor operating characteristics of the memory device, analyze the monitored operating characteristics, detect a precursor to a memory failure based on the analysis, and manage redundant sections in the plurality of memory sections based on the detected precursor.

27. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory elements; and

the control logic is operable to monitor writes to the plurality of memory elements of the non-volatile memory array, and allocate as redundant sections ones of the plurality of memory sections characterized by write endurance.

28. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array including a plurality of memory elements; and

the control logic is operable to monitor writes to the plurality of memory elements of the non-volatile memory array, and allocate as redundant sections ones of the plurality of memory sections that have a history of fewer writes.

29. The memory device according to claim 1 wherein:

the memory array includes at least one non-volatile memory array that is partitioned into a plurality of memory blocks; and

the control logic is partitioned into a plurality of command logic blocks spatially distributed over the non-volatile memory array wherein ones of the plurality of command logic blocks are associated with ones of the plurality of memory blocks.

30. The memory device according to claim 1 wherein:

the control logic is operable to operate in combination with the non-volatile memory array to accumulate information about a product.

31. A method of operating a memory device comprising:

providing a memory array including a plurality of memory sections characterized by a plurality of memory types;

providing a control logic integrated with and distributed over the memory array; and

operating the control logic to selectively allocate redundant sections in the plurality of memory sections.

32. A memory system comprising:

means for storing information in a memory array including a plurality of memory sections characterized by a plurality of memory types;

means integrated with and distributed over the memory array for controlling the means for storing information; and

means for selectively allocating redundant sections in the plurality of memory sections.

33. A system comprising:

circuitry for storing information in a memory array including a plurality of memory sections characterized by a plurality of memory types;

circuitry integrated with and distributed over the memory array for controlling the means for storing information; and

circuitry for selectively allocating redundant sections in the plurality of memory sections.